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PDF LRS1B12 Data sheet ( Hoja de datos )
| Número de pieza | LRS1B12 | |
| Descripción | 64M ( X16) Flash & 64M ( X16) Flash & 32M ( X16) SCRAM & 8M (x16) SRAM | |
| Fabricantes | Sharp Microelectronics | |
| Logotipo |  |
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Date Mar. 5. 2003
64M (x16) Flash + 64M (x16) Flash
32M (x16) SCRAM + 8M (x16) SRAM
LRS1B12
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LRS1B12
3
1. Description
The LRS1B12 is a combination memory organized as 4,194,304 x16 bit flash memory, 4,194,304 x16 bit flash memory,
2,097,152 x16 bit Smartcombo RAM and 524,288 x16 bit static RAM in one package.
Features
-Power supply
• • • • 2.7V to 3.1V
-Operating temperature
• • • • -25°C to +85°C
-Not designed or rated as radiation hardened
-72 pin CSP(LCSP072-P-0811) plastic package
-Flash memory has P-type bulk silicon, and Smartcombo RAM has P-type bulk silicon, and SRAM has P-type bulk silicon
-Flash memory and Smartcombo RAM share one power supply pin (F/SC-VCC)
-For specifications of Flash memory, Smartcombo RAM and SRAM, refer to specification of each chip
Standby current of Flash memory and Smartcombo RAM
-Power supply current
• • • • 150 µA (Max.)
Flash Memory 1 (F1: 64M (x16) bit Flash Memory)
-Access Time (Address)
••••
-Power supply current (The current for F/SC-VCC pin and VPP pin)
Read
••••
Word write
••••
Block erase
••••
65 ns (Max.)
25 mA
60 mA
30 mA
(Max. tCYCLE = 200ns, CMOS Input)
(Max.)
(Max.)
Flash Memory 2 (F2: 64M (x16) bit Flash Memory)
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-Access Time (Address)
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-Power supply current (The current for F/SC-VCC pin and VPP pin)
Read
••••
Word write
••••
Block erase
••••
65 ns
25 mA
60 mA
30 mA
(Max.)
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(Max. tCYCLE = 200ns, CMOS Input)
(Max.)
(Max.)
Smartcombo RAM (32M (x16) bit Smartcombo RAM)
-Access Time (Address)
-Cycle time
-Power Supply current
Operating current
••••
••••
65 ns
65 ns
(Max.)
(Min.)
• • • • 50 mA (Max. tRC, tWC = Min.)
SRAM (8M (x16) bit SRAM)
-Access Time (Address)
-Power Supply current
Operating current
Standby current
• • • • 65 ns (Max.)
••••
••••
45 mA (Max. tRC, tWC = Min.)
15 µA (Max.)
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LRS1B12
9
6.1.2 Simultaneous Operation Modes Allowed with Four Planes (1,2)
THEN THE MODES ALLOWED IN THE OTHER PARTITION IS:
IF ONE
PARTITION IS: Read
Array
Read ID
Read
Status
Read
Query
Word
Program
Page
Buffer
Program
Block
Erase
Full Chip Program
Erase Suspend
Read Array
X
X
X
X
X
X
X
X
Block
Erase
Suspend
X
Read ID
X
X
X
X
X
X
X
XX
Read Status
X
X
X
X
X
X
X
X
X
X
Read Query
X
X
X
X
X
X
X
Word Program X X X X
Page Buffer
Program
X
X
X
X
XX
X
X
Block Erase
X
X
X
X
Full Chip Erase
X
Program
Suspend
X
X
X
X
X
Block Erase
Suspend
X
X
X
X
X
X
X
Notes:
1. “X” denotes the operation available.
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2. Configurative Partition Dual Work Restrictions:
Status register reflects partition state, not WSM (Write State Machine) state - this allows a status register for each partition.
Only one partition can be erased or programmDedaatat Sa htiemeet4-Uno.ccoommmand queuing.
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Commands must be written to an address within the block targeted by that command.
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11 Page | ||
| Páginas | Total 70 Páginas | |
| PDF Descargar | [ Datasheet LRS1B12.PDF ] | |
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