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CS5828 데이터시트 PDF




Myson Technology에서 제조한 전자 부품 CS5828은 전자 산업 및 응용 분야에서
광범위하게 사용되는 반도체 소자입니다.


PDF 형식의 CS5828 자료 제공

부품번호 CS5828 기능
기능 28:4 LVDS Transmitter
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CS5828 데이터시트, 핀배열, 회로
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28:4 LVDS Transmitter
CS5828
GENERAL DESCRIPTION
The CS5828 receives four sets of 7-bit data in
CMOS logic level and converts them into four low-
voltage differential signaling (LVDS) serial channels.
The 7-bit input data is referenced to the CKIN signal.
The RF pin selects either rising or falling edge trigger
of CKIN. Parallel to serial conversion is performed by
a 7X internal generated clock reference using on-
chip PLL using CKIN. A copy of CKIN but phase-
locked to the output serial streams, CLKOUT, is also
converted to the fifth LVDS channel. The CS5828
offers a reliable communication media using LVDS
signaling and provides low EMI dealing with wide,
high-speed TTL interfaces.
This is especially attractive for interfaces between
GUI controller and display systems such as LCD
panels for SVGA/XGA/SXGA applications.
FEATURES
• Four 7-bit serial and one clock LVDS channels.
• Compatible with ANSI TIA/EIA-644 LVDS stan-
dard.
• Wide CKIN ranges from 31MHz to 85MHz.
• Fully integrated on-chip PLL that provides 7X
CKIN serial shift clock.
• Pin selectable for rising or falling edge trigger.
• Support power-down mode.
• 5V/3.3V tolerant data input.
• Single 3.3V supply operation.
• CMOS low power consumption.
• Functional compatible with DS90C385.
• Available in 56-pin TSSOP package.
BLOCK DIAGRAM
D0,D1,D2,D3,
D4,D6,D7
D8,D9,D12,D13,
D14,D15,D18
D19,D20,D21,D22,
D24,D25,D26
D27,D5,D10,D11,
D16,D17,D23
RF
CKIN
SHTDN
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DIN PARALLEL-IN SERIAL-OUT
SHIFT/LOAD_N7-Bit SHIFT REGISTER
CLK
DIN PARALLEL-IN SERIAL-OUT
SHIFT/LOAD_N7-Bit SHIFT REGISTER
CLK
DIN PARALLEL-IN SERIAL-OUT
SHIFT/LOAD_N7-Bit SHIFT REGISTER
CLK
DIN PARALLEL-IN SERIAL-OUT
7-Bit SHIFT REGISTER
SHIFT/LOAD_N
CLK
7xCLK
PHASE LOCK LOOP
SHIFT/LOAD_N
R/F
CLK
CONTROL LOGIC
CS5828
Y0P
EN
Y0N
Y1P
EN
Y1N
Y2P
EN
Y2N
Y3P
EN
Y3N
CKOP
EN
CKON
DataShee
Myson Century, Inc.
Taiwan:
No. 2, Industry East Rd. III,
DataSheet4SUci.ecnocme-Based Industrial Park, Hsin-Chu, Taiwan
Tel: 886-3-5784866 Fax: 886-3-5784349
USA:
4020 Moorpark Avenue Suite 115
San Jose, CA, 95117
Tel: 408-243-8388 Fax: 408-243-3188
www.myson.com.tw
Rev.1.4 August 2002
page 1 of 13
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CS5828 pdf, 반도체, 판매, 대치품
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CS5828
FUNCTIONAL DESCRIPTION
Control logic
There are two modes in this circuit. One is normal mode, and another is power down mode. Two modes are
controlled by the control signal “SHTDN”. If SHTDN is high, the circuit is in the normal mode, else if low, the
circuit is in the power down mode. In the power down mode, every block is off to make sure the least power
consumption.
7 x CLK PLL
7 x CLK PLL, which is a phase lock loop, generates seven times clock of CKIN. The signal “RF” indicates that the
input data (D0 ~ D27) is rising edge or falling edge trigger by CKIN. If RF=1, it is rising edge trigger, else if RF=0,
it is falling trigger. This seven times clock of CKIN is used by the Parallel ~ LOAD 7 Bit shift Register. 7 x CLK PLL
also generate the control signal “SHIFT/LOAD”. This signal is also used by the Parallel ~ LOAD 7 Bit Shift
Register to indicate when to load data or shift data.
Parallel ~ LOAD 7 Bit shift Register
This block transfers 7 bits parallel data into one bit series data out. It is controlled by SHIFT/LOAD. If this control
signal is low, the data are loaded into shift registers. Next, the SHIFT/LOAD turns high to shift data from shift
register to output buffer seven times. One load and then seven shift.
Ref:
There are two properties in this block. One is that it supports reference voltage to fine the output’s common mode
voltage. Another is that it generates about (4ns ~6ns) pulse width’s power on reset signal. When power on, all
block would be reset by power on reset signal to make sure that the circuit would not stuck-at some situation we
do not care.
et4U.com Output buffer
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DataShee
There are four data output buffers and one clock output buffer. Output buffer generates differential pair output
that swing is under 500 ~ 900mV, and common-mode voltage is under 1.125V ~ 1.375V.
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CS5828 전자부품, 판매, 대치품
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AC CHARACTERISTICS
Symbol
Parameter
Condition
t0 CKOto bit 0
Tc= 11.76 ns
t1 CKOto bit 1
t2 CKOto bit 2
t3 CKOto bit 3
t4 CKOto bit 4
t5 CKOto bit 5
t6 CKOto bit 6
tskew
tc(o)
Output skew
Cycle time, Output clock jitter
tw Pulse duration, high-level output
clock
tt
tenable
Transition time, differential output
voltage (tr or tf)
Enable time, SHTDNto phase lock
(Yn valid)
tdisable
Disable time, SHTDNto off state
(CKO low)
et4U.com
DataSheet4U.com
CS5828
Min
-0.2
1/7tc-0.2
2/7tc-0.2
3/7tc-0.2
4/7tc-0.2
5/7tc-0.2
6/7tc-0.2
-0.2
-
Typ
0
-
-
-
-
-
-
-
±100
Max
0.2
1/7tc+0.2
2/7tc+0.2
3/7tc+0.2
4/7tc+0.2
5/7tc+0.2
6/7tc+0.2
0.2
-
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ps
- 4/7tc -
ns
260 700 1500 ps
- 1 - ms
- 250 - ns
DataShee
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