PDF CS5825 Data sheet ( Hoja de datos )

Número de pieza	CS5825
Descripción	28:4 LVDS Receiver
Fabricantes	Myson Technology
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No Preview Available ! www.DataSheet4U.com Century Semiconductor Inc. CS5825 28:4 LVDS Receiver GENERAL DESCRIPTION CS5825 receives four LVDS data channels and one LVDS clock channel. Each data channel is deserialized into 7-bit parallel data bus for output. The clock channel is used for frame sync and fed into an internal PLL that generates the 7X serial clock used in the deserializer. A digital phase alignment circuit can generate the sampling clock of the deserializer front-end. The frame sync clock aligned to the output 7-bit data is also output for timing reference. CS5825 supports open-safe design of LVDS when the input is not connected to LVDS drivers and the receiver outputs are forced low. Putting CS5825 into inhibit mode by a shutdown control (SHTDNN) signal can lower power consumption. FEATURES • Four 7-bit serial data LVDS channels and one clock LVDS channel. • Compatible with ANSI TIA/EIA-644 LVDS stan- dard. • Wide serial clocking speed ranges from 31MHz to 68MHz. • Support open-safe LVDS design. • Fully integrated on-chip PLL and digital phase alignment provide accurate deserializer operation. • Support power-down mode. • 5V/3.3V tolerant data input. • Single 3.3V supply operation. • CMOS low power consumption. • Functional compatible with DS90CF384 and SN75LVDS86. • Available in 56-pin TSSOP package. BLOCK DIAGRAM CS5825 AIP AIM BIP BIM CIP CIM DIP DIM CKIP CKIM SHTDNN DIN CLK DataSheet4U.com PARALLEL-IN SERIAL-OUT 7-Bit SHIFT REGISTER DIN CLK DIN CLK DIN CLK 7xCLK PARALLEL-IN SERIAL-OUT 7-Bit SHIFT REGISTER PARALLEL-IN SERIAL-OUT 7-Bit SHIFT REGISTER PARALLEL-IN SERIAL-OUT 7-Bit SHIFT REGISTER PHASE LOCK LOOP AND PHASE ALIGNER CONTROL LOGIC CS5825 D0,D1,D2,D3, D4,D6,D7 D8,D9,D12,D13, D14,D15,D18 D19,D20,D21,D22, D24,D25,D26 D27,D5,D10,D11, D16,D17,D23 CLKOUT DataShee Century Semiconductor, Inc. Taiwan: No. 2, Industry East Rd. 3rd, Science-Based Industrial Park, Hsin-Chu, Taiwan Tel: 886-3-5784866 Fax: 886-3-5784349 DataSheet4U.com USA: 1485 Saratoga Ave. #200 San Jose, CA, 95129 Tel: 408-973-8388 Fax: 408-973-9388 [email protected] [email protected] www.century-semi.com Rev.0.0 May 2001 page 1 of 13 DataSheet4 U .com DataSheet4U.com 1 page www.DataSheet4U.com Century Semiconductor Inc. Recommended Operating Conditions Symbol Parameter VCC VIH(SHTDN) VIL(SHTDN) Supply voltage High-level input voltage Low-level input voltage Receiver input range TA Operating free-air temperature Min Typ 3 3.3 2- -- 0- 0- CS5825 Max 3.6 - 0.8 2.4 70 Unit V V V V °C Timing Requirements Symbol Parameter tc Cycle time, input clock* tsu1 Setup time, input th1 Hold time, input Min Typ Max Unit 14.7 tc 32.4 ns 600 - - ps 600 - - ps Note: Parameter tc is defined as the mean duration of a minimum of 32000 clock cycles. et4U.com Electrical Characteristics over recommended operating conditions (unless otherwise noted) Symbol Parameter Condition Min Typ Max VIT+ Differential input high threshold voltageDataSheet4U.com VIT- Differential input low threshold voltage - - 100 -100 - - VOH High-level output voltage VOL Low-level output voltage IOH = -4mA 2.4 - - IOL = 4mA - - 0.4 Disabled (power down mode), All inputs open - 280 - ICC Quiescent current (average) IIH High-level input current (SHTDN) IIL Low-level input current (SHTDN) Enabled, AnP = 1V, AnM = 1.4V, tc = 15.38ns Enabled, CL = 8 pF, Grayscale pattern, tc = 15.38ns Enabled, CL = 8 pF, Grayscale pattern, tc = 15.38ns VIH = VCC VIL = 0 - - - - - 58 72 69 - 94 - - ±20 - ±20 II Input current (LVDS input terminals A and CLKIN) 0 ≤ V1 ≤ 2.4V - - ±10 IOZ High-impedance output current VO = 0 or VCC - - ±10 Unit mV DataShee mV V V µA mA mA mA µA µA µA µA DataSheet4U.com DataSheet4 U .com page 5 of 13 DataSheet4U.com 5 Page www.DataSheet4U.com Century Semiconductor Inc. CS5825 CKIP/CKIM CLKOUT Vdiff=0v CCD Figure-9 Clock-in to Clock-out Delay et4U.com Power Down Vcc CKIP/CKIM RxCLK OUT 2V 3V PLLs DataSheet4U.com 2V Figure-10 Phase Lock Loop Stable Time Power Down (Low Active) 1.5V RxCLK In RxOUT PDD Figure-11 Power Down Delay Low DataShee DataSheet4U.com DataSheet4 U .com page 11 of 13 DataSheet4U.com 11 Page

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