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74FCT541 데이터시트 PDF




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74FCT541 데이터시트, 핀배열, 회로
®
Integrated Device Technology, Inc.
FAST CMOS OCTAL
BUFFER/LINE DRIVER
IDT54w/7w4w.FDCataTSh2e4et04U/A.co/mC
IDT54/74FCT241/A/C
IDT54/74FCT244/A/C
IDT54/74FCT540/A/C
IDT54/74FCT541/A/C
FEATURES:
• IDT54/74FCT240/241/244/540/541 equivalent to FASTTM
speed and drive
• IDT54/74FCT240A/241A/244A/540A/541A 25% faster
than FAST
• IDT54/74FCT240C/241C/244C/540C/541C up to 55%
faster than FAST
• IOL = 64mA (commercial) and 48mA (military)
• CMOS power levels (1mW typ. static)
• Product available in Radiation Tolerant and Radiation
Enhanced versions
• Military product compliant to MIL-STD-883, Class B
• Meets or exceeds JEDEC Standard 18 specifications
DESCRIPTION:
The IDT octal buffer/line drivers are built using an advanced
dual metal CMOS technology. The IDT54/74FCT240/A/C,
IDT54/74FCT241/A/C and IDT54/74FCT244/A/C are designed
to be employed as memory and address drivers, clock drivers
and bus-oriented transmitter/receivers which provide improved
board density.
The IDT54/74FCT540/A/C and IDT54/74FCT541/A/C are
similar in function to the IDT54/74FCT240/A/C and IDT54/
74FCT244/A/C, respectively, except that the inputs and out-
puts are on opposite sides of the package. This pinout
arrangement makes these devices especially useful as output
ports for microprocessors and as backplane drivers, allowing
ease of layout and greater board density.
FUNCTIONAL BLOCK DIAGRAMS
2529 cnv* 01–03
OEA
OEB
DA0
OA0
OB0
DB0
DA1
OB1
OA1
DB1
DA2
OB2
OA2
DB2
DA3
OA3
OB3
DB3
OEA
DA0
OB0
DA1
OB1
DA2
OB2
DA3
OB3
241 Only
OEB*
OA0
DB0
OA1
DB1
OA2
DB2
OA3
DB3
OEA
D0
D1
D2
D3
D4
D5
D6
D7
OEB
O0*
O1*
O2*
O3*
O4*
O5*
O6*
O7*
IDT54/74FCT240
IDT54/74FCT241/244
*OEB for 241, OEB for 244
IDT54/74FCT540/541
*Logic diagram shown for 'FCT540.
'FCT541 is the non-inverting option.
2606 dwg 01–03
The IDT logo is a registered trademark of Integrated Device Technology, Inc.
FAST is a trademark of National Semiconductor Co.
MILITARY AND COMMERCIAL TEMPERATURE RANGES
©1992 Integrated Device Technology, Inc.
7.8
MAY 1992
DSC-4610/3
1




74FCT541 pdf, 반도체, 판매, 대치품
IDT54/74FCT240/241/244/540/541/A/C
FAST CMOS OCTAL BUFFER/LINE DRIVER
MILITARY AND COMMERCIAL TEMPERATURE RANGES
www.DataSheet4U.com
DC ELECTRICAL CHARACTERISTICS OVER OPERATING RANGE
Following Conditions Apply Unless Otherwise Specified: VLC = 0.2V; VHC = VCC – 0.2V
Commercial: TA = 0°C to +70°C, VCC = 5.0V ± 5%; Military: TA = –55°C to +125°C, VCC = 5.0V ± 10%
Symbol
VIH
Parameter
Input HIGH Level
Test Conditions(1)
Guaranteed Logic HIGH Level
Min. Typ.(2) Max. Unit
2.0 — —
V
VIL Input LOW Level
Guaranteed Logic LOW Level
— — 0.8 V
II H Input HIGH Current
II L Input LOW Current
VCC = Max.
VI = VCC
VI = 2.7V
VI = 0.5V
— — 5 µA
— — 5(4)
— — –5(4)
VI = GND
— — –5
IOZH
IOZL
Off State (High Impedance)
Output Current
VCC = Max.
VO = VCC
VO = 2.7V
VO = 0.5V
— — 10 µA
— — 10(4)
— — –10(4)
VO = GND
— — –10
VIK Clamp Diode Voltage
IOS Short Circuit Current
VCC = Min., IN = –18mA
VCC = Max.(3), VO = GND
— –0.7 –1.2 V
–60 –120 — mA
VOH Output HIGH Voltage
VCC = 3V, VIN = VLC or VHC, IOH = –32µA
VHC VCC
V
VCC = Min.
IOH = –300µA
VHC VCC
VIN = VIH or VIL
IOH = –12mA MIL.
2.4 4.3 —
IOH = –15mA COM'L. 2.4 4.3
VOL Output LOW Voltage
VCC = 3V, VIN = VLC or VHC, IOL = 300µA
VCC = Min.
IOL = 300µA
— GND VLC
V
— GND VLC(4)
VIN = VIH or VIL
IOL = 48mA MIL.
— 0.3 0.55
IOL = 64mA COM'L.
— 0.3 0.55
NOTES:
1. For conditions shown as Max. or Min., use appropriate value specified under Electrical Characteristics for the applicable device type.
2. Typical values are at VCC = 5.0V, +25°C ambient and maximum loading.
3. Not more than one output should be shorted at one time. Duration of the short circuit test should not exceed one second.
4. This parameter is guaranteed but not tested.
2606 tbl 03
7.8 4

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74FCT541 전자부품, 판매, 대치품
IDT54/74FCT240/241/244/540/541/A/C
FAST CMOS OCTAL BUFFER/LINE DRIVER
TEST CIRCUITS AND WAVEFORMS
TEST CIRCUITS FOR ALL OUTPUTS
VCC 7.0V
VIN
Pulse
Generator
V OUT
D.U.T.
500
50pF
500
RT CL
MILITARY AND COMMERCIAL TEMPERATURE RANGES
www.DataSheet4U.com
SWITCH POSITION
Test
Switch
Open Drain
Disable Low
Enable Low
Closed
All Other Tests
Open
DEFINITIONS:
2606 tbl 10
CL = Load capacitance: includes jig and probe capacitance.
RT = Termination resistance: should be equal to ZOUT of the Pulse
Generator.
SET-UP, HOLD AND RELEASE TIMES
DATA
INPUT
TIMING
INPUT
ASYNCHRONOUS CONTROL
PRESET
CLEAR
ETC.
SYNCHRONOUS CONTROL
PRESET
CLEAR
CLOCK ENABLE
ETC.
t SU
t SU
tH
t REM
tH
PULSE WIDTH
3V
1.5V
0V
3V
1.5V
0V
LOW-HIGH-LOW
PULSE
3V
1.5V
0V
HIGH-LOW-HIGH
PULSE
3V
1.5V
0V
1.5V
tW
1.5V
PROPAGATION DELAY
SAME PHASE
INPUT TRANSITION
OUTPUT
OPPOSITE PHASE
INPUT TRANSITION
tPLH
t PLH
t PHL
tPHL
3V
1.5V
0V
VOH
1.5V
VOL
3V
1.5V
0V
ENABLE AND DISABLE TIMES
ENABLE
CONTROL
INPUT
OUTPUT
NORMALLY
LOW
t PZL
SWITCH
CLOSED
t PZH
OUTPUT SWITCH
NORMALLY OPEN
HIGH
3.5V
1.5V
1.5V
0V
DISABLE
tPLZ
3V
1.5V
0V
3.5V
t PHZ
0.3V V OL
0.3V V OH
0V
NOTES
2606 drw 10
1. Diagram shown for input Control Enable-LOW and input Control
Disable-HIGH.
2. Pulse Generator for All Pulses: Rate 1.0 MHz; ZO 50; tF 2.5ns;
tR 2.5ns.
7.8 7

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