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기능 (RD38F4455LVY / RD38F4050L0Z) Wireless Memory System
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RD38F4455LVY 데이터시트, 핀배열, 회로
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Intel StrataFlash£ Wireless Memory
System (LV18/LV30 SCSP)
768-Mbit LVQ Family with Asynchronous Static RAM
Datasheet
Product Features
Device Architecture
xRAM Performance
— Code and data segment: 128- and 256-
Mbit density; PSRAM: 32- and 64-Mbit
density; SRAM: 8 Mbit density.
— PSRAM at 1.8 V I/O : 85 ns initial
access, 30 ns async page reads; 65 ns
initial access, 18 ns async page.
— Top or bottom parameter configuration. — SRAM at 1.8 or 3.0 V I/O: 70 ns initial
— Asymmetrical blocking structure.
access.
— 16-KWord parameter blocks (Top or
Flash Performance
Bottom); 64-K Word main blocks.
— Code Segment at 1.8 V I/O: 85 ns initial
— Zero-latency block locking.
access; 25 ns async page read; 14 ns
— Absolute write protection with block
sync reads (tCHQV); 54 MHz CLK.
lock down using F-WP#.
— Data Segment at 1.8 V I/O: 170 ns initial
access; 55 ns async page read.
Device Voltage
— Core: VCC = 1.8 V (typ).
Flash Architecture
— Hardware Read-While-Write/Erase.
— I/O: VCCQ = 1.8 V or 3.0DVa(ttaySph).eet4U.com— 8-Mbit or 16-Mbit Multi-Partition.
Device Concurrent Operations (3 Dies)
— Buffered EFP: 600 KB per second.
— 2-Kbit One-Time Programmable (OTP)
Protection Register.
— Erase Performance: 384 KB per second
(main blocks).
— Software Read-While-Write/Erase.
Device Packaging
— Single Full-Die Partition size.
— 88 balls (8 x 10 active ball matrix).
— Area: 8 x 10 mm or 8 x 11 mm.
Flash Software
— Intel£ FDI, Intel£ PSM, and Intel£
VFM.
— Height: 1.0 mm to 1.4 mm.
— Common Flash Interface (CFI).
Quality and Reliability
— Extended Temp: 25 °C to +85 °C.
— Basic/Extended Command Set.
— Minimum 100 K flash block erase cycle.
The Intel StrataFlash® Wireless Memory System (LV18/LV30 SCSP); 768-Mbit LVQ Family
with Asynchronous Static RAM device offers a high performance code and large embedded data
segment plus RAM combination in a common package with electrical QUAD+ ballout on 0.13
µm ETOX™ VIII flash technology. The code segment flash die features 1.8 V low-power
operations with flexible, multi-partition, dual operation Read-While-Write / Read-While-Erase,
asynchronous and synchronous burst reads at 54 MHz. The data segment flash die features 1.8 V
low-power operations optimized for cost sensitive asynchronous data applications. This device
integrates up to three flash dies, two PSRAM dies, and one SRAM die in a low-profile package
compatible with other SCSP families using the QUAD+ ballout package.
Notice: This document contains information on new products in production. The specifications
are subject to change without notice. Verify with your local Intel sales office that you have the lat-
est datasheet before finalizing a design.
253852-002
December 2003
DataShee
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Contents
et4U.com
10.0 Flash Read Operation ................................................................................................................. 37
11.0 Flash Program Operation ........................................................................................................... 37
12.0 Flash Erase Operation ................................................................................................................ 37
13.0 Flash Suspend and Resume Operations................................................................................... 37
14.0 Flash Block Locking and Unlocking Operations...................................................................... 37
15.0 Flash Protection Register Operation ......................................................................................... 37
16.0 Flash Configuration Operation................................................................................................... 37
17.0 Dual Operation Considerations.................................................................................................. 38
17.1 Product Configurations and Memory Partitioning ............................................................... 38
17.2 Product Segment Unique Features .................................................................................... 39
17.3 Flash Die Memory Map....................................................................................................... 40
18.0 PSRAM Operations...................................................................................................................... 45
18.1 PSRAM Power-up Sequence and Initialization................................................................... 45
18.2 PSRAM Mode Register....................................................................................................... 45
18.2.1 PSRAM Mode Register Setting ............................................................................. 46
18.2.2 Cautions for Setting PSRAM Mode Register ......................................................... 47
18.3 PSRAM Low-Power Mode .................................................................................................. 48
Appendix A Write State Machine ........................................................................................................ 49
Appendix B Common Flash Interface......D...a..t.a..S..h..e..e..t.4..U.....c..o..m................................................................ 49
Appendix C Flash Flowcharts ............................................................................................................. 49
Appendix D Additional Information .................................................................................................... 50
Appendix E Ordering Information....................................................................................................... 51
DataShee
Revision History
Date
10/03r
12/03
Revision
-001
-002
Description
Initial Release
In the Valid Combinations Table: Added line item mehcanical
and ordering information for 256L+256V+64P+64P. Deleted
the TBD 5-die stack option. Revised the Matrix table.
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768-Mbit LVQ Family with Asynchronous Static RAM
1.2 Acronyms
et4U.com
Buffered-EFP
CUI
OTP
PLR
PR
RCR
RFU
SR
WSM
APS
CFI
MLC technology
RWE
RWW
Buffered Enhanced Factory Programming
Command User Interface
One-Time Programmable
Protection Lock Register
Protection Register
Read Configuration Register
Reserved for Future Use (all unused active signals in a package ballout)
Status Register
Write State Machine
Automatic Power Savings
Common Flash Interface
Multi-Level-Cell technology
Read-While-Erase
Read-While-Write
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1.3 Conventions
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Datasheet
VCC
Signal or voltage connection
VCC Signal or voltage level
Set Logical one (1)
Clear
Logical zero (0)
0x Hexadecimal number prefix
0b Binary number prefix
SR[4]
Denotes an individual flash status register bit, in this case bit 5 of
SR[7:0].
D[15:0]
Denotes a group of similarly named signals, such as data bus.
A5 Denotes one element of a signal group membership, in this case address
bit 5.
F[3:1]-CE#, F[2:1]-OE# This is the method used to refer to more than one chip-enable or output
enable at the same time. When each is referred to individually, the
reference will be F1-CE# and F1-OE# (for die #1), F2-CE# and F2-OE#
(for die #2), and F3-CE# and F3-OE#(for die #3). “F” denotes the flash
specific signal and “CE#” is the root signal name of the flash die. Other
7
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RD38F4455LVY

(RD38F4455LVY / RD38F4050L0Z) Wireless Memory System

Intel
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