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부품번호 | A1225A 기능 |
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기능 | (A1225A - A1280A) FPGAs | ||
제조업체 | Actel | ||
로고 | |||
전체 30 페이지수
www.DataSheet4U.com
v4.0.1
ACT™ 2 Family FPGAs
Features
• Up to 8000 Gate Array Gates
(20,000 PLD equivalent gates)
• Replaces up to 200 TTL Packages
• Replaces up to eighty 20-Pin PAL® Packages
• Design Library with over 500 Macro Functions
• Single-Module Sequential Functions
• Wide-Input Combinatorial Functions
• Up to 1232 Programmable Logic Modules
• Up to 998 Flip-Flops
• Datapath Performance at 105 MHz
• 16-Bit Accumulator Performance to 39 MHz
• Two In-Circuit Diagnostic Probe Pins Support Speed
Analysis to 50 MHz
• Two High-Speed, Low-Skew Clock Networks
• I/O Drive to 10 mA
• Nonvolatile, User Programmable
• Logic Fully Tested Prior to Shipment
• 1.0-micron CMOS Technology
Product Family Profile
Device
A1225A
A1240A
A1280A
Capacity
Gate Array Equivalent Gates
PLD Equivalent Gates
TTL Equivalent Packages
20-Pin PAL Equivalent Packages
2,500
6,250
DataSheet46U3.com
25
4,000
10,000
100
40
8,000
20,000
200
80
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Logic Modules
S-Modules
C-Modules
451 684 1,232
231 348 624
220 336 608
Flip-Flops (maximum)
382 568 998
Routing Resources
Horizontal Tracks/Channel
Vertical Tracks/Channel
PLICE Antifuse Elements
36
15
250,000
36
15
400,000
36
15
750,000
User I/Os (maximum)
Packages1
Performance2
16-Bit Prescaled Counters
16-Bit Loadable Counters
16-Bit Accumulators
83
100 CPGA
100 PQFP
100 VQFP
84 PLCC
105 MHz
70 MHz
39 MHz
104
132 CPGA
144 PQFP
176 TQFP
84 PLCC
100 MHz
69 MHz
38 MHz
140
176 CPGA
160 PQFP
176 TQFP
84 PLCC
172 CQFP
85 MHz
67 MHz
36 MHz
Notes:
1. See the “Product Plan” on page 3 for package availability.
2. Performance is based on ‘–2’ speed devices at commercial worst-case operating conditions using PREP Benchmarks, Suite #1, Version 1.2,
dated 3-28-93, any analysis is not endorsed by PREP.
DataSheet4U.com
December 2000
DataSheet 4 U .c©o2m000 Actel Corporation
DataSheet4U.com
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ACT™ 2 Family FPGAs
Operating Conditions
Absolute Maximum Ratings1
Free air temperature range
Symbol
Parameter
Limits
Units
VCC DC Supply Voltage
VI Input Voltage
VO Output Voltage
IIO
I/O Source/Sink
Current2
–0.5 to +7.0
–0.5 to VCC +0.5
–0.5 to VCC +0.5
±20
V
V
V
mA
TSTG Storage Temperature –65 to +150
°C
Notes:
1. Stresses beyond those listed under “Absolute Maximum
Ratings” may cause permanent damage to the device.
Exposure to absolute maximum rated conditions for extended
periods may affect device reliability. Device should not be
operated outside the Recommended Operating Conditions.
2. Device inputs are normally high impedance and draw
extremely low current. However, when input voltage is greater
than VCC + 0.5 V or less than GND – 0.5 V, the internal
protection diode will be forward biased and can draw excessive
current.
Recommended Operating Conditions
Commercia Industria
Parameter
l
l Military Units
Temperature
Range1
0 to +70
–40 to
+85
–55 to
+125
°C
Power
Supply
±5 ±10 ±10 %VCC
Tolerance
Note:
1. Ambient temperature (TA) is used for commercial and
industrial; case temperature (TC) is used for military.
Electrical Specifications
et4U.com
Commercial
Industrial
Military
Symbol
Parameter
Min. DatMaaSxh.eet4U.Mcoinm.
Max.
Min.
Max.
VOH1
(IOH = –10 mA) 2
(IOH = –6 mA)
VOL1
(IOH = –4 mA)
(IOL = 10 mA) 2
(IOL = 6 mA)
VIL
VIH
Input Transition Time tR, tF2
CIO I/O Capacitance2, 3
Standby Current, ICC4 (typical = 1 mA)
Leakage Current5
2.4
3.84
3.7 3.7
0.5
0.33 0.40 0.40
–0.3 0.8 –0.3 0.8 –0.3 0.8
2.0 VCC + 0.3 2.0 VCC + 0.3 2.0 VCC + 0.3
500 500 500
10 10 10
2 10 20
–10 10 –10 10 –10 10
Notes:
1. Only one output tested at a time. VCC = min.
2. Not tested, for information only.
3. Includes worst-case 176 CPGA package capacitance. VOUT = 0 V, f = 1 MHz.
4. All outputs unloaded. All inputs = VCC or GND, typical ICC = 1 mA. ICC limit includes IPP and ISV during normal operation.
5. VOUT , VIN = VCC or GND.
Units
V
V
V
V
V
V
V
ns
pF
mA
µA
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ACT™ 2 Family FPGAs
ACT 2 Timing Model*
et4U.com
Input Delays
Internal Delays
I/O Module
tINYL = 2.6 ns
Combinatorial
Logic Module
tIRD2 = 4.8 ns†
Predicted
Routing
Delays
Output Delays
I/O Module
DQ
G
tINH = 2.0 ns
tINSU = 4.0 ns
tINGL = 4.7 ns
ARRAY
CLOCKS
tCKH = 11.8 ns
FMAX = 100 MHz
FO = 256
tPD = 3.8 ns
tRD1 = 1.4 ns
tRD2 = 1.7 ns
tRD4 = 3.1 ns
tRD8 = 4.7 ns
Sequential
Logic Module
tDLH = 8.0 ns
I/O Module
tDLH = 8.0 ns
Combin-
atorial
Logic
included
in tSUD
tSUD = 0.4 ns
tHD = 0.0 ns
DQ
tRD1 = 1.4 ns
DQ
G
tENHZ = 7.1 ns
tCO = 3.8 ns
tOUTH = 0.0 ns
tOUTSU = 0.4 ns
tGLH = 9.0 ns
DataShee
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*Values shown for A1240A-2 at worst-case commercial conditions.
† Input Module Predicted Routing Delay
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구매 문의 | 일반 IC 문의 : 샘플 및 소량 구매 ----------------------------------------------------------------------- IGBT, TR 모듈, SCR 및 다이오드 모듈을 포함한 광범위한 전력 반도체를 판매합니다. 전력 반도체 전문업체 상호 : 아이지 인터내셔날 사이트 방문 : [ 홈페이지 ] [ 블로그 1 ] [ 블로그 2 ] |
부품번호 | 상세설명 및 기능 | 제조사 |
A1225 | Hall Effect Latch for High Temperature Operation | Allegro MicroSystems |
A1225A | (A1225A - A1280A) FPGAs | Actel |
DataSheet.kr | 2020 | 연락처 | 링크모음 | 검색 | 사이트맵 |