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PDF AT89LP213 Data sheet ( Hoja de datos )
| Número de pieza | AT89LP213 | |
| Descripción | 8-bit Microcontroller | |
| Fabricantes | ATMEL Corporation | |
| Logotipo |  |
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Features
• 8-bit Microcontroller Compatible with MCS®51 Products
• Enhanced 8051 Architecture
– Single Clock Cycle per Byte Fetch
– Up to 20 MIPS Throughput at 20 MHz Clock Frequency
– Fully Static Operation: 0 Hz to 20 MHz
– On-chip 2-cycle Hardware Multiplier
– 128 x 8 Internal RAM
– 4-level Interrupt Priority
• Nonvolatile Program Memory
– 2K Bytes of In-System Programmable (ISP) Flash Memory
– Endurance: Minimum 10,000 Write/Erase Cycles
– Serial Interface for Program Downloading
– 32-byte Fast Page Programming Mode
– 64-byte User Signature Array
– 2-level Program Memory Lock for Software Security
• Peripheral Features
– Two 16-bit Enhanced Timer/Counters
– Two 8-bit PWM Outputs (AT89LP213 Only)
– Enhanced UART with Automatic Address Recognition and Framing Error
Detection (AT89LP214 Only)
– Enhanced Master/Slave SPI with Double-buffered Send/Receive
– Programmable Watchdog Timer with Software Reset
– Analog Comparator with Selectable Interrupt and Debouncing
– 8 General-purpose Interrupt Pins
• Special Microcontroller Features
– Two-wire On-chip Debug Interface
– Brown-out Detection and Power-on Reset with Power-off Flag
– Internal 8 MHz RC Oscillator
– Low Power Idle and Power-down Modes
– Interrupt Recovery from Power-down Mode
• I/O and Packages
– Up to 12 Programmable I/O Lines
– Configurable I/O with Quasi-bidirectional, Input, Push-pull Output, and
Open-drain Modes
– 5V Tolerant I/O
– 14-lead TSSOP or PDIP
• Operating Conditions
– 2.4V to 5.5V VCC Voltage Range
– -40° C to 85°C Temperature Range
8-bit
Microcontroller
with 2K Bytes
Flash
AT89LP213
AT89LP214
1. Description
The AT89LP213/214 is a low-power, high-performance CMOS 8-bit microcontroller
with 2K bytes of In-System Programmable Flash memory. The device is manufactured
using Atmel's high-density nonvolatile memory technology and is compatible with the
industry-standard MCS-51 instruction set. The AT89LP213/214 is built around an
enhanced CPU core that can fetch a single byte from memory every clock cycle.
In the classic 8051 architecture, each fetch requires 6 clock cycles, forcing instruc-
tions to execute in 12, 24 or 48 clock cycles. In the AT89LP213/214 CPU, instructions
3538E–MICRO–11/10
1 page  
4. Block Diagram
Figure 4-1. AT89LP213 Block Diagram
AT89LP213/214
Single Cycle
8051 CPU
2KB Flash
128 Bytes
RAM
Port 3
Configurable I/O
Port 1
Configurable I/O
General-purpose
Interrupt
SPI
Timer 0
Timer 1
Analog
Comparator
Watchdog
Timer
On-Chip
RC Oscillator
CPU Clock Configurable
Oscillator
Figure 4-2. AT89LP214 Block Diagram
Crystal or
Resonator
Single Cycle
8051 CPU
2KB Flash
128 Bytes
RAM
Port 3
Configurable I/O
Port 1
Configurable I/O
General-purpose
Interrupt
CPU Clock
UART
SPI
Timer 0
Timer 1
Analog
Comparator
Watchdog
Timer
On-Chip
RC Oscillator
Configurable
Oscillator
Crystal or
Resonator
3538E–MICRO–11/10
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5 Page 
AT89LP213/214
Figure 8-3. Two-cycle ALU Operation (Example: ADD A, #data)
T1 T2
System Clock
Total Execution Time
Fetch Immediate Operand
ALU Operation Execute
Result Write Back
Fetch Next Instruction
T3
8.1 Restrictions on Certain Instructions
The AT89LP213/214 is an economical and cost-effective member of Atmel's growing family of
microcontrollers. It contains 2K bytes of Flash program memory. It is fully compatible with the
MCS-51 architecture, and can be programmed using the MCS-51 instruction set. However,
there are a few considerations one must keep in mind when utilizing certain instructions to pro-
gram this device. All the instructions related to jumping or branching should be restricted such
that the destination address falls within the physical program memory space of the device, which
is 2K for the AT89LP213/214. This should be the responsibility of the software programmer. For
example, LJMP 7E0H would be a valid instruction, whereas LJMP 900H would not.
8.1.1
Branching Instructions
The LCALL, LJMP, ACALL, AJMP, SJMP, and JMP @A+DPTR unconditional branching instruc-
tions will execute correctly as long as the programmer keeps in mind that the destination
branching address must fall within the physical boundaries of the program memory size (loca-
tions 000H to 7FFH for the AT89LP213/214). Violating the physical space limits may cause
unknown program behavior. With the CJNE [...], DJNZ [...], JB, JNB, JC, JNC, JBC, JZ, and JNZ
conditional branching instructions, the same previous rule applies. Again, violating the memory
boundaries may cause erratic execution. For applications involving interrupts the normal inter-
rupt service routine address locations of the 8051 family architecture have been preserved.
8.1.2
MOVX-related Instructions, Data Memory
The AT89LP213/214 contains 128 bytes of internal data memory. RAM accesses to addresses
above 7FH will return invalid data. Furthermore, the stack depth is limited to 128 bytes, the
amount of available RAM. The Stack Pointer should not be allowed to point to locations above
7FH. External DATA memory access is not supported in this device, nor is external PROGRAM
memory execution. Therefore, no MOVX [...] instructions should be included in the program.
A typical 8051 assembler will still assemble instructions, even if they are written in violation of
the restrictions mentioned above. It is the responsibility of the user to know the physical features
and limitations of the device being used and to adjust the instructions used accordingly.
3538E–MICRO–11/10
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| Páginas | Total 30 Páginas | |
| PDF Descargar | [ Datasheet AT89LP213.PDF ] | |
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