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PDF TXC-05802B Data sheet ( Hoja de datos )
| Número de pieza | TXC-05802B | |
| Descripción | ATM DATA-LINK SWITCHING/ROUTING | |
| Fabricantes | Transwitch | |
| Logotipo |  |
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CUBIT®-Pro Device
CellBus® Bus Switch
TXC-05802B
DATA SHEET
FEATURES
DESCRIPTION
• UTOPIA and 16-Bit (ATM or PHY) Layer cell inter- CUBIT-ProTM is a single-chip solution for implementing
faces
• Inlet-side address translation and routing header
insertion, using external SRAM of up to 256 kB
• Programmable OAM-cell and RM-cell routing
• CellBus bus access request, grant reception and
bus transmission
• CellBus bus cell reception and address recognition
• Outlet cell queuing: various modes
cost effective ATM access systems. It is based on the
CellBus® Bus Architecture (CellBus). Such systems are
constructed from a number of CUBIT-Pro devices, all
interconnected by a 37-line common bus, the CellBus
bus. When operating at a 38 MHz clock rate, a CellBus
bus system can handle 1 Gbit/s of net ATM cell band-
width. CUBIT-Pro supports unicast and multicast trans-
fers, and has all necessary functions for implementing a
switch: cell address translation, cell routing, and outlet
• Ability to insert GFC field in real time
cell queuing.
• Ability to insert FECN indication, under program-
mable conditions
• Ability to send and receive cells for control purpos-
es over same CellBus bus
The TXC-05802B has GTL+ drivers with improved slew
rate control. This ensures CellBus compatibility with new
generations of CellBus devices. The TXC-05802B is a
functional replacement for the TXC-05802 and is tar-
• Cell insertion and extraction via microprocessor
geted for GTL+ applications. It can operate with dual 5 V
port and 3.3 V supplies, or a single 3.3 V supply.
• Master bus arbiter and frame pulse generator in-
cluded in each CUBIT-Pro, with enabling pin
APPLICATIONS
• Improved internal GTL+ transceivers for CellBus
bus connection
DataShee•t4xUD.ScoLmAccess Multiplexer
• Interface port to translation table in SRAM
• Remote Access Equipment
• Microprocessor control port, selectable for Intel or • Cable Modem Access Multiplexer
Motorola interface
• ATM LAN hub
• +5 V and +3.3 V power supplies (dual-supply op-
eration) or single-supply +3.3 V operation
• ATM multiplexer/concentrator
• Small-stand-alone ATM switch
• 208-pin plastic quad flat package (28 x 28 mm)
• Add-Drop Ring Switch
• Edge switching equipment
DataShee
Translation RAM
Address 18 8 Data 2 Control
Cell Inlet
Data
Other
8
4
CUBIT-Pro
Cell Outlet
Data
Other
8
8
22
Clock, controls, test, etc.
CellBus Bus Switch
TXC-05802B
37
2
CellBus Bus Port (32-bit data)
Other CellBus bus-related signals
Address 8
8 Data 7 Controls and clock input
U.S. Patents No. 5,568,060; 5,901,146
Microprocessor Port
U.S. and/or foreign patents issued or pending
Copyright 2001 TranSwitch Corporation
CUBIT-Pro is a trademark of TranSwitch Corporation
TranSwitch, TXC, CellBus, CUBIT and SALI-25C are registered trademarks of Tran-
DataSheet4US.wciotcmh Corporation
TranSwitch Corporation • 3 Enterprise Drive • Shelton, Connecticut 06484
Tel: 203-929-8810 • Fax: 203-926-9453 • www.transwitch.com
Document Number:
TXC-05802B-MB
Ed. 3, February 2001
• USA
DataSheet4 U .com
1 page  
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Proprietary TranSwitch Corporation Information for use Solely by its Customers
DATA SHEET
CUBIT-Pro
TXC-05802B
BLOCK DIAGRAM
et4U.com
8
CID(7-0)
CICLAV
CICLK
CIENB
PHYEN
Translation
Control
External Translation RAM Port
Address TRA(17-0)
Reset
and Test
Data TRD(7-0)
TROE
TRWE
6
Inlet Queue
Data Cell Queue
4 cells
Cell
Inlet
Port
Control Queue
1 cell
Loopback Queue
1 cell
CISOC
Outlet Queue
8
COD(7-0)
COCLAV
COCLK
COENB
Cell
Outlet
Port
Synchronization FIFO
3 cells
Loopback Queue
1 cell
Data Cell Queue
123
cells
DaCtoanStrohl eQeuetu4eU.com
4 cells
Cell
Address
Screen
COSOC
4
GFC(3-0)
88
Microprocessor Interface
FRCABRCNG
Address Data
LCLOCK A(7-0) D(7-0)
INT/ RDY/
IRQ DTACK
RD or
RD/WR
WR
SEL PCLK
MOTO
CBDISABLE
VREF
CellBus
Bus
Interface
Logic
CellBus Bus Port
32
CBD(31-0)
CBRC
CBWC
CBF
CBACK
CBCONG
Bus
Arbiter
and
Frame
Pulse
Generator
12
ENARB
Other Controls
DataShee
Figure 1. CUBIT-Pro TXC-05802B Block Diagram
A block diagram of the CUBIT-Pro device is shown in Figure 1. Further information on device operation and
the interfaces to external circuits is provided below in the following Operation section.
On the cell inlet side of the CUBIT-Pro is circuitry associated with accepting cells from the line and passing
them to the CellBus bus with an appropriate header. The Cell Inlet Port block is pin-selectable to be compliant
with either the ATM Forum UTOPIA (Universal Test and Operations Physical Interface for ATM) interface, or a
TranSwitch 16-Bit interface. Incoming cells may carry a CellBus Routing Header and translated outgoing
VPI/VCI address, the translation function having been performed externally, or this address translation and
routing header insertion may be done by the CUBIT-Pro Translation Control block. Translation and routing
header tables to support this function are contained in an external static RAM (up to 256k x 8 bits). They sup-
port VPI and/or VPI/VCI address translation. The incoming cells then pass through a FIFO queue in the Inlet
Queue block to the CellBus Bus Port via the CellBus Bus Interface Logic block. When there is a cell in this 4-cell
data cell queue, the CUBIT-Pro makes a bus access request, and waits for a grant from the Bus Arbiter and
Frame Pulse Generator block of the one CUBIT-Pro device attached to the bus that has been enabled to per-
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TXC-05802B-MB
Ed. 3, February 2001
5 Page 
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DATA SHEET
CUBIT-Pro
TXC-05802B
et4U.com
both directions. It is calculated over the 12-bit word (X11-X0) in bits 31-20 of the Routing Header using the
following logic:
Η3 = (Χ7 ⊕ Χ9 ⊕ Χ3 ⊕ Χ10 ⊕ Χ8 ⊕ Χ5 ⊕ Χ2)
Η2 = (Χ6 ⊕ Χ8 ⊕ Χ2 ⊕ Χ9 ⊕ Χ7 ⊕ Χ4 ⊕ Χ1)
Η1 = (Χ5 ⊕ Χ7 ⊕ Χ1 ⊕ Χ8 ⊕ Χ6 ⊕ Χ3 ⊕ Χ0)
Η0 = (Χ8 ⊕ Χ10 ⊕ Χ11 ⊕ Χ4 ⊕ Χ9 ⊕ Χ6 ⊕ Χ3 ⊕ Χ0)
where ⊕ represents logical exclusive-or. For cells arriving from the CellBus bus, the CUBIT-Pro automatically
calculates the corresponding CRC-4 and sets to 1 the status bit CRCF (bit 7 in register 08H) if it is not the
same as that in bits H3-H0 of the received Routing Header. This status bit may be enabled to cause an inter-
rupt signal to the microprocessor by setting to 1 the enable bit INTEN7 (bit 7 in register 09H). For cells supplied
to the cell inlet interface from an external source for transmission via the CellBus bus, the CRC-4 may either be
supplied in the input signal by use of external logic (as is required for the CUBIT device) or it may be generated
internally and inserted into the Routing Header by the CUBIT-Pro. Setting control bit CRC4EN to 1 (bit 3 in reg-
ister 0EH) activates the internal CRC-4 insertion for all incoming cells (i.e., not only data cells, but also control
cells and loopback cells). When control bit CRC4I (bit 4 in register 0EH) is set to 1 the internally generated
CRC-4 is inverted for testing purposes. This bit has no effect on an externally-supplied CRC-4. For operation in
the CUBIT TXC-05801 mode with an externally-supplied CRC-4, bit CRC4EN should be set to 0, which is the
default at power-up/reset.
Tandem Routing Header Format
The two-byte Tandem Routing Header format in Bits 15-0 of Cycle 1 is the same as the CellBus Bus Routing
Header format, if it is to be used by a cascaDdaetdaSChelelBeut4sUb.ucso,mor may conform to a different specification if it is
used by another system. The Tandem Routing Header is passed unchanged through the CellBus bus.
DataShee
CellBus Bus Status Signals and Monitoring
The CUBIT-Pro provides the capability to monitor the activity on the CellBus bus. The essential signals that
determine whether the bus is active (in the absence of any cell traffic) are the clock signals and the frame
pulse.
The CellBus bus clocks (read and write) are generated externally to the CUBIT-Pro. If either of these clocks
fails, the entire bus will cease operation. The CUBIT-Pro provides the capability to detect the absence of clock
signal for more than the equivalent of 32 processor clock (PCLK) cycles. The failure detection is performed
independently for the CellBus Bus Read Clock (CBRC) and the CellBus Bus Write Clock (CBWC).
Two bits (register 05H bits CBLORC and CBLOWC) in the CUBIT-Pro memory map are used to indicate the
clock loss event. Once the event is detected, these bits in register 05H will remain set to one until the micropro-
cessor reads the register, at which point the register will be cleared. These events can be used to generate a
microprocessor interrupt provided that the appropriate bits in the interrupt enable register (address 06H, bits
INTENA1 and INTENA0) are 1.
The second monitoring function concerns the detection of loss of frame. The detection mechanism looks for
two consecutive missing CellBus bus frame pulses in 32-user mode (U32 = Low), and four consecutive missing
CellBus bus frame pulses in 16-user mode. The CellBus Bus Read Clock must be present to detect Loss of
Frame Pulse. If CellBus Bus Read Clock is present and CellBus Bus Write Clock is not, then both CBLOWC and
CBLOF will be set. CBLOF can generate an interrupt to the microprocessor assuming that the appropriate
interrupt enable bit is 1 (register 06H, bit 2: INTENA2).
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TXC-05802B-MB
Ed. 3, February 2001
11 Page | ||
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| PDF Descargar | [ Datasheet TXC-05802B.PDF ] | |
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