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PDF TXC-05806 Data sheet ( Hoja de datos )
| Número de pieza | TXC-05806 | |
| Descripción | ATM DATA-LINK SWITCHING/ROUTING | |
| Fabricantes | Transwitch | |
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ASPEN Express Device
Multi-PHY CellBus Access Device
TXC-05806
DATA SHEET
FEATURES
DESCRIPTION
• 622 Mbit/s bi-directional throughput
• UTOPIA Level 1/2 interface (8/16-bit) with support
for 64/124 ports at 50 MHz
• OAM Fault Management per ITU-T I.610
• UPC/NPC policing on ingress compliant with
TM4.1
• Early Packet Discard (EPD) and Partial Packet
Discard (PPD) in inlet and outlet direction
• Dual CellBus interfaces for load sharing or
redundancy
• Inlet-side address translation and routing header
insertion
• Header translation for egress cells
• 512k cell shared SDRAM buffer memory
• Support for spatial multicast for 512 sessions with
header translation
• Support for over-reservation of GFR, UBR, and
VBR traffic
The ASPEN Express device is a single-chip solution for
implementing cost-effective ATM multiplexing and switching
systems, based on the CellBus architecture. Such systems are
constructed from a number of CUBIT-3, CUBIT-Pro,
CUBIT-622, or ASPEN devices, all interconnected by a 37-line
common bus, the CellBus. The ASPEN Express provides state
of the art traffic management to the CellBus family of ATM
switching devices. ASPEN Express supports unicast and
multicast transfers, and has all necessary functions for
implementing a switch: cell address translation, cell routing,
policing and inlet/outlet cell queuing. The ASPEN Express
offers dual CellBus interfaces to support load sharing or
redundancy.
The ASPEN Express is designed to interface directly with
UTOPIA Level 1/2, 8/16-bit compliant devices, such as the
PHAST-3P (TXC-06203) and the PHAST-12E (TXC-06212) at
up to 50 MHz. On the switch side, the ASPEN Express
interfaces directly with CellBus devices such as the CUBIT-Pro
(TXC-05802B), CUBIT-3 (TXC-05804), CUBIT-622
• Minimum Cell Rate (MCR) guarantees for egress
(TXC-05805) and ASPEN (TXC-05810B).
queues
• CellBus traffic monitor mode including APS
APPLICATIONS
support and congestion control
DataShe•et4ATUM.coAmccess Multiplexers
• Cell insertion and extraction via microprocessor
interface port
• DSLAM Applications
• Microprocessor control port, selectable for Intel,
• Remote Access Equipment
Motorola 360 or Motorola MPC 860 interfaces
• ATM LAN Switch
• Test Access Port for IEEE 1149.1 boundary scan
• +3.3 V I/O and +1.8 V core power supplies
• Frame Relay Switch
• 456-lead Plastic Ball Grid Array (PBGA) package,
27 mm x 27 mm
DataShee
PHY SIDE
Connection Table SDRAM
SWITCH SIDE
UTOPIA Inlet
Data
Addr/Ctl
UTOPIA Outlet
Data
Addr/Ctl
Clock, controls, test, etc.
Row/Col 15 32 Data 6
16
14 ASPEN Express
Controls
6
Controls
32
Multi-PHY
Data
15
16 CellBus Access Device Row/Col
14 TXC-05806
37
37
CellBus Port A (32-bit data)
CellBus Port B (32-bit data)
Address 8 16 Data 6
Controls
U.S. Patent No. 5,568,060, 5,901,146
Microprocessor Port
Copyright 2003 TranSwitch Corporation
ASPEN Express is a trademark of TranSwitch Corporation
DataSheetT4rUan.Scwoimtch, TXC, ASPEN, CellBus, CUBIT and PHAST
are registered trademarks of TranSwitch Corporation
Document Number:
PRELIMINARY TXC-05806-MB, Ed. 7
October 2003
TranSwitch Corporation • 3 Enterprise Drive • Shelton, Connecticut 06484 • USA
Tel: 203-929-8810 • Fax: 203-926-9453 • www.transwitch.com
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Proprietary TranSwitch Corporation Information for use Solely by its Customers
DATA SHEET
ASPEN Express
TXC-05806
BLOCK DIAGRAM DESCRIPTION
Cell Inlet to CellBus
On the cell inlet side of the ASPEN Express is circuitry associated with accepting cells from the line and
passing them to the CellBus with an appropriate header. The Cell Inlet Port block is selectable to be compatible
with either the ATM Forum UTOPIA (Universal Test and Operations Physical Interface for ATM) Level 1 or 2
interface. Incoming cells may be translated using the ASPEN Express. Translation and routing header tables
to support this function are contained in an external SDRAM (up to 64k connections). There is support for VPI,
or VPI/VCI address translation. Lookup is supported for up to 600 VPIs within the full 4096 VPI range. Each
port can be configured independently for 2 consecutive ranges of VPIs. Different PHYs can use overlapping
ranges of VPI. Each VPI is then configured to support 2 ranges of VCI. The total number of VCIs supported
cannot exceed 64k. Different VPIs can use overlapping ranges of VCI.
Each VCI can be configured for UPC. Full TM4.1 support for policing is provided utilizing two 32-bit GCRA
engines implementing the Virtual Scheduling Algorithm with a 20 ns resolution clock.
Ingress and egress queues share a 512k cell buffer in SDRAM and utilize a decoupling FIFO for each CellBus.
The ingress queuing consists of 8 priority queues for each CellBus. Queue limits are enforced for each queue
via dynamic buffer allocation.
et4U.com
A 6-cell FIFO receives all cells from the UTOPIA bus. The ASPEN Express can process a full 622 Mbit/s of
ingress traffic while also processing 622 Mbit/s of egress traffic from the CellBus. Higher bandwidth can be
processed at the ingress if a corresponding lower bandwidth is required from the egress (asymmetric
application).
DataShee
When the ASPEN Express has a cell pendinDgaitnaSohneeeotf4Uits.cinogmress queues, it makes a CellBus access request,
and upon receiving a grant will send the cell to the CellBus in standard CellBus format. In addition to data cells,
the ASPEN Express can also send control cells from the local microprocessor to the bus. Diagnostic loopback
cells received from the CellBus may be looped back to the CellBus to a designated CellBus device/queue. Both
the control cells and the loopback cells have inlet queues consisting of FIFOs with a depth of two cells and one
cell, respectively.
Local switching is supported so that cells received from the UTOPIA can be directly queued to egress queues
and routed back to another (or the same) UTOPIA address.
A count is kept for total numbers of invalid cells received. An invalid cell is one in which the VPI or VCI is out of
range of the configured lookup table. Registers hold Port, VPI and VCI of the last invalid cell received.
Misrouted cells are defined as connections whose active bit has not been set; a count is kept for all misrouted
cells. Per VC statistics include cell count, non-conforming cells for GCRA1, and non-conforming cells for
GCRA2 as well as buffer discard counts for each connection and each queue.
Early Packet Discard (EPD) and Partial Packet Discard (PPD) are ATM cell discard techniques which maximize
the transmission of whole packets (goodput) for AAL5 adapted packet traffic. These techniques minimize
transmission of partial packets since these represent wasted bandwidth; any cells dropped from a packet
require the retransmission of the entire packet by the network. Both EPD and PPD are supported (per VCC) for
ingress and egress. The ingress connection table will hold the packet discard state for ingress connections
(VCCs). A separate packet discard state machine will keep track of packet discard states for each VCC in the
connection table. If a cell is discarded (either due to UPC/NPC or queue full) and packet discard is enabled, the
connection drops all remaining cells of the packet. A separate EPD queue threshold triggers EPD for all new
packets received while the queue threshold exceeds this level.
Segment or end-end OAM cells for selected VCCs (F5) or VPCs (F4) may be selectively routed to the OAM
processor. The OAM processor handles all OAM-FM functions per ITU-T I.610 including AIS, RDI, Continuity
Check, and Loopback. All loopback cells can be routed to the host processor. Management flows are identified
by assigning them to the host extraction queue; all management cells are extracted to the host.
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PRELIMINARY TXC-05806-MB, Ed. 7
October 2003
5 Page 
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Proprietary TranSwitch Corporation Information for use Solely by its Customers
DATA SHEET
ASPEN Express
TXC-05806
et4U.com
ATM TxData
TxSOC
TxClav
TxEnb
TxClk
TxParity
RxData
RxSOC
RxClav
RxEnb
RxClk
RxParity
16
VSS
16
VSS
UI_D(15-0)
UI_SOC
UI_CLAV(3-0)
UI_ENB(3-0)
UI_CLKI
UI_PARITY
UI_ADDR(4-0)
ASPEN Express
UO_D(15-0)
UO_SOC
UO_CLAV(3-0)
UO_ENB(3-0)
UO_CLKI
UO_PARITY
UO_ADDR(4-0)
CBA_D(31-0) 32
CBA_RC
CBA_WC
CBA_F
CBA_ACK
CBA_CONG
CBB_D(31-0) 32
CBB_RC
CBB_WC
CBB_F
CBB_ACK
CBB_CONG
CellBus A
CellBus B
Figure 7. ASPEN Express Device in PHY Layer, Single-PHY Mode Configuration
PHY RxData
RxSOC
RxClav
RxEnb
RxClk
RxParity
RxAddr
TxData
TxSOC
TxClav
TxEnb
TxClk
TxParity
TxAddr
16 DataSheet4U.com
UI_D(15-0)
UI_SOC
CBA_D(31-0) 32
CBA_RC
UI_CLAV(3-0)
UI_ENB(3-0)
UI_CLKO
CBA_WC
CBA_F
CellBus A
UI_CLKI
CBA_ACK
UI_PARITY
5 UI_ADDR(4-0)
CBA_CONG
ASPEN Express
16 CBB_D(31-0) 32
UO_D(15-0)
UO_SOC
CBB_RC
UO_CLAV(3-0)
UO_ENB(3-0)
CBB_WC
CellBus B
UO_CLKO
CBB_F
UO_CLKI
UO_PARITY
CBB_ACK
5
UO_ADDR(4-0)
CBB_CONG
Figure 8. ASPEN Express Device in ATM Layer, Multi-PHY Mode Configuration
DataShee
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- 11 of 92 -
PRELIMINARY TXC-05806-MB, Ed. 7
October 2003
11 Page | ||
| Páginas | Total 30 Páginas | |
| PDF Descargar | [ Datasheet TXC-05806.PDF ] | |
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