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PDF TXC-05860 Data sheet ( Hoja de datos )
| Número de pieza | TXC-05860 | |
| Descripción | UTOPIA Serializer | |
| Fabricantes | Transwitch | |
| Logotipo |  |
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Sertopia™ Device
UTOPIA Serializer
TXC-05860
TECHNICAL OVERVIEW
PRODUCT PREVIEW
FEATURES
DESCRIPTION
• UTOPIA Level 2, UTOPIA 2P, and POS-PHY operating
modes for cell and packet traffic
• One UTOPIA port (800 Mbit/s)
• Two serial ports (channels A and B, one for primary and
the other for redundant, with each at 1.25 Gbit/s)
• Backward compatible with UTOPIA Level 1
• UTOPIA port configurable as master or slave
• Up to 32 UTOPIA PHY addresses supported
• Configurable cell size of 52 to 64 bytes
• Configurable packet chunk size of 16, 48, or 64 bytes in
UTOPIA 2P mode
• Transparent backpressure mechanism to avoid cell or
packet loss
• Operation with a single 125 MHz reference clock
• CRC generation on transmit and verification on receive
• On-line and off-line loopback modes for serial and
UTOPIA ports
• In-band configuration and status report
The Sertopia™ (TXC-05860) UTOPIA serializer is a single-chip
solution for broadband communication systems. A pair of
Sertopia devices interface two remote UTOPIA ports
transparently across a serial link. The Sertopia emulates a
UTOPIA Level 2 master or UTOPIA Level 2 slave and contains
a SERDES (serializer/deserializer) which transfers the cell or
packet along with the UTOPIA port information. The Sertopia
can emulate an ATM or PHY layer device on the UTOPIA bus. If
backpressure for a given PHY is sensed on the UTOPIA port,
the Sertopia conveys this backpressure (in-band) to the remote
Sertopia, which holds traffic destined for that port until the
backpressure is released. The Sertopia is also configurable
through in-band signaling by a remote host controller. The
Sertopia provides error check for all pass-through traffic in both
directions. It discards any corrupted cells or packets without
propagating errors. Instead, it reports error status to a remote
host controller via internally generated signaling cells. The
Sertopia enables UTOPIA Level 2 devices to communicate
seamlessly across line cards, shelves, and racks without
additional logic. Together with TranSwitch’s CUBIT, ASPEN, and
AsTriX family devices, and other standard UTOPIA devices, the
Sertopia device can be used to create a cost effective point-to-
point serial backplane-based access system.
• Built in self test (BIST)
APPLICATIONS
• I(nTtXeCro-p0e5r8a0b5le),wAitShPCEUNB®IT(T®-X3C(T-0X5C81-005),80A4s)T,rCiXU™BIT®-6D22ataShe•etR4eUm.cootemAccess Concentrators
• Multi-service Access Systems
(TXC-05840), and standard UTOPIA level 2 interface
devices
• Digital Cross Connect Systems
• Test Access Port for IEEE 1149.1 boundary scan
• DSLAM Applications
• +3.3 V and +1.8 V power supplies
• Wireless Base Station Systems
• 196-lead Plastic Ball Grid Array package (PBGA),
• Routers
15 mm x 15 mm
• Aggregation of multiple CellBus shelves
DataShee
Clock, controls, test, etc.
UTOPIA Level 2 Port
Sertopia
UTOPIA Serializer
TXC-05860
Channel A Serial Port
Channel B Serial Port
Copyright 2001 TranSwitch Corporation
Sertopia and AsTriX are trademarks of TranSwitch Corporation
DataSheetT4rUan.Scwoimtch, TXC, CellBus, CUBIT and ASPEN are
registered trademarks of TranSwitch Corporation
Document Number:
PRODUCT PREVIEW TXC-05860-MA
Ed. 2, October 2001
TranSwitch Corporation • 3 Enterprise Drive • Shelton, Connecticut 06484 • USA
Tel: 203-929-8810 • Fax: 203-926-9453 • www.transwitch.com
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Proprietary TranSwitch Corporation Information for use Solely by its Customers
TECHNICAL OVERVIEW
Sertopia
TXC-05860
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The TX/RX Link Control modules and the Flow Control module guarantee reliable data transmission across the
serial interface. The Device In-Band Configuration module provides an interface for power-on and on-the-fly
configuration. It sets an interface mode between cell, packet or POS-PHY operations, PHY addressing
scheme, PHY address range, cell/chunk size, etc. The Local and Remote Loopback Buffers allow non-disrup-
tive loopback, without interfering with normal traffic. The Clock and PLL blocks generate ITCLK and ETCLK,
allowing the Sertopia to be a clock source for the UTOPIA interface, when in UTOPIA master mode. The
8B/10B interface block is used to support a third party SerDes transceiver or optical fiber transceiver. The RST
module controls device reset and the JTAG module provides boundary scan for Sertopia. The Indication mod-
ule provides device status indications.
UTOPIA INTERFACE CONFIGURATION
The Sertopia’s UTOPIA Interface can be configured for either Cell Mode or Packet Mode. It supports standard
UTOPIA 2 for cell mode and either UTOPIA 2P or POS-PHY for packet mode.
In UTOPIA Cell Mode, the Sertopia device supports the following configurations:
- UTOPIA Master/Slave
- UTOPIA 8-bit Mode/16-bit Mode
- UTOPIA Single-PHY/Multi-PHY
- Programmable Cell Size from 52 bytes to 64 bytes
- Addressing mode (single or dual group)
- Address range (0 - 30 for single address group mode or 0 - 15 for dual address group mode. The
start address is always 0)
In UTOPIA Packet Mode, the Sertopia device DsuaptapSorhtesetht4eUf.oclolomwing configurations:
- UTOPIA 2P Packet Mode/POS-PHY Packet Mode
- UTOPIA Master/Slave
- UTOPIA Single-PHY/Multi-PHY
- Programmable Chunk Sizes of 16, 48, or 64 bytes
- Addressing mode (single or dual group)
- Address range (0 - 30 for single address group mode or 0 - 15 for dual address group mode. The
start address is always 0)
Only 16-bit mode is supported under the packet mode.
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PRODUCT PREVIEW TXC-05860-MA
Ed. 2, October 2001
5 Page 
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Proprietary TranSwitch Corporation Information for use Solely by its Customers
TECHNICAL OVERVIEW
Sertopia
TXC-05860
REFERENCE DOCUMENTS
• The ATM Forum: UTOPIA Specification Level 1, Version 2.0.1, March 1994.
• The ATM Forum: UTOPIA Specification Level 2, Version 1.0, June 1995.
• IEEE 1149.1 Standard Test Access Port and Boundary-Scan Architecture, May 1990.
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PRODUCT PREVIEW TXC-05860-MA
Ed. 2, October 2001
11 Page | ||
| Páginas | Total 16 Páginas | |
| PDF Descargar | [ Datasheet TXC-05860.PDF ] | |
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