20N06 - NTD20N06

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NTD20N06

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NTD20N06

Power MOSFET

20 Amps, 60 Volts, N−Channel DPAK

Designed for low voltage, high speed switching applications in

power supplies, converters and power motor controls and bridge

circuits.

Features

• Pb−Free Packages are Available

• Lower RDS(on)

• Lower VDS(on)

• Lower Capacitances

• Lower Total Gate Charge

• Lower and Tighter VSD

• Lower Diode Reverse Recovery Time

• Lower Reverse Recovery Stored Charge

Typical Applications

• Power Supplies

• Converters

• Power Motor Controls

• Bridge Circuits

MAXIMUM RATINGS (TJ = 25°C unless otherwise noted)

Rating

Symbol Value Unit

Drain−to−Source Voltage

Drain−to−Gate Voltage (RGS = 10 MW)

Gate−to−Source Voltage

− Continuous

− Non−repetitive (tpv10 ms)

Drain Current

− Continuous @ TA = 25°C

− Continuous @ TA = 100°C

− Single Pulse (tpv10 ms)

Total Power Dissipation @ TA = 25°C

Derate above 25°C

Total Power Dissipation @ TA = 25°C (Note 1)

Total Power Dissipation @ TA = 25°C (Note 2)

Operating and Storage Temperature Range

VDSS

VDGR

VGS

IDM

TJ, Tstg

"20

"30

0.40

1.88

1.36

−55 to

175

Vdc

Adc

Apk

W/°C

°C

Single Pulse Drain−to−Source Avalanche

Energy − Starting TJ = 25°C

(VDD = 25 Vdc, VGS = 10 Vdc,

L = 1.0 mH, IL(pk) = 18.4 A, VDS = 60 Vdc)

Thermal Resistance

− Junction−to−Case

− Junction−to−Ambient (Note 1)

− Junction−to−Ambient (Note 2)

Maximum Lead Temperature for Soldering

Purposes, 1/8″ from case for 10 seconds

EAS

RqJC

RqJA

170 mJ

°C/W

2.5

110

260 °C

Maximum ratings are those values beyond which device damage can occur.

Maximum ratings applied to the device are individual stress limit values (not

normal operating conditions) and are not valid simultaneously. If these limits

are exceeded, device functional operation is not implied, damage may occur

and reliability may be affected.

1. When surface mounted to an FR4 board using the minimum recommended

pad size.

2. When surface mounted to an FR4 board using the 0.5 sq in drain pad size.

August, 2004 − Rev. 6

http://onsemi.com

V(BR)DSS

60 V

RDS(on) TYP

37.5 mW

ID MAX

20 A

N−Channel

MARKING

DIAGRAMS

Drain

DPAK

CASE 369C

STYLE 2

Gate

Drain

Source

DPAK−3

CASE 369D

STYLE 2

Drain

12 3

Gate Drain Source

20N06

= Device Code

= Assembly Location

= Year

= Work Week

ORDERING INFORMATION

See detailed ordering and shipping information in the package

dimensions section on page 2 of this data sheet.

Publication Order Number:

NTD20N06/D

www.DataSheet4U.com

NTD20N06

POWER MOSFET SWITCHING

Switching behavior is most easily modeled and predicted

by recognizing that the power MOSFET is charge

controlled. The lengths of various switching intervals (Dt)

are determined by how fast the FET input capacitance can

be charged by current from the generator.

The published capacitance data is difficult to use for

calculating rise and fall because drain−gate capacitance

varies greatly with applied voltage. Accordingly, gate

charge data is used. In most cases, a satisfactory estimate of

average input current (IG(AV)) can be made from a

rudimentary analysis of the drive circuit so that

t = Q/IG(AV)

During the rise and fall time interval when switching a

resistive load, VGS remains virtually constant at a level

known as the plateau voltage, VSGP. Therefore, rise and fall

times may be approximated by the following:

tr = Q2 x RG/(VGG − VGSP)

tf = Q2 x RG/VGSP

where

VGG = the gate drive voltage, which varies from zero to VGG

RG = the gate drive resistance

and Q2 and VGSP are read from the gate charge curve.

During the turn−on and turn−off delay times, gate current is

not constant. The simplest calculation uses appropriate

values from the capacitance curves in a standard equation for

voltage change in an RC network. The equations are:

td(on) = RG Ciss In [VGG/(VGG − VGSP)]

td(off) = RG Ciss In (VGG/VGSP)

The capacitance (Ciss) is read from the capacitance curve at

a voltage corresponding to the off−state condition when

calculating td(on) and is read at a voltage corresponding to the

on−state when calculating td(off).

At high switching speeds, parasitic circuit elements

complicate the analysis. The inductance of the MOSFET

source lead, inside the package and in the circuit wiring

which is common to both the drain and gate current paths,

produces a voltage at the source which reduces the gate drive

current. The voltage is determined by Ldi/dt, but since di/dt

is a function of drain current, the mathematical solution is

complex. The MOSFET output capacitance also

complicates the mathematics. And finally, MOSFETs have

finite internal gate resistance which effectively adds to the

resistance of the driving source, but the internal resistance

is difficult to measure and, consequently, is not specified.

The resistive switching time variation versus gate

resistance (Figure 9) shows how typical switching

performance is affected by the parasitic circuit elements. If

the parasitics were not present, the slope of the curves would

maintain a value of unity regardless of the switching speed.

The circuit used to obtain the data is constructed to minimize

common inductance in the drain and gate circuit loops and

is believed readily achievable with board mounted

components. Most power electronic loads are inductive; the

data in the figure is taken with a resistive load, which

approximates an optimally snubbed inductive load. Power

MOSFETs may be safely operated into an inductive load;

however, snubbing reduces switching losses.

2000

VDS = 0 V VGS = 0 V

1600 Ciss

1200

Crss

800

TJ = 25°C

Ciss

400

10 5 0 5

VGS

VDS

Crss

10 15

Coss

20 25

GATE−TO−SOURCE OR DRAIN−TO−SOURCE VOLTAGE (VOLTS)

Figure 7. Capacitance Variation

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NTD20N06

PACKAGE DIMENSIONS

DPAK

CASE 369C−01

ISSUE O

−T−

SEATING

PLANE

1 23

D 2 PL

G 0.13 (0.005) M T

SOLDERING FOOTPRINT*

6.20

0.244

2.58

0.101

3.0

0.118

5.80

0.228

1.6 6.172

0.063 0.243

INCHES

DIM MIN MAX

A 0.235 0.245

B 0.250 0.265

C 0.086 0.094

D 0.027 0.035

E 0.018 0.023

F 0.037 0.045

G 0.180 BSC

H 0.034 0.040

J 0.018 0.023

K 0.102 0.114

L 0.090 BSC

R 0.180 0.215

S 0.025 0.040

U 0.020 −−−

V 0.035 0.050

Z 0.155 −−−

STYLE 2:

PIN 1. GATE

2. DRAIN

3. SOURCE

4. DRAIN

MILLIMETERS

MIN MAX

5.97 6.22

6.35 6.73

2.19 2.38

0.69 0.88

0.46 0.58

0.94 1.14

4.58 BSC

0.87 1.01

0.46 0.58

2.60 2.89

2.29 BSC

4.57 5.45

0.63 1.01

0.51 −−−

0.89 1.27

3.93 −−−

ǒ ǓSCALE 3:1

inches

*For additional information on our Pb−Free strategy and soldering

details, please download the ON Semiconductor Soldering and

Mounting Techniques Reference Manual, SOLDERRM/D.

http://onsemi.com

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