PDF MC68HC16Z1 Data sheet ( Hoja de datos )

Número de pieza	MC68HC16Z1
Descripción	Single Chip Microcontrollers
Fabricantes	Motorola Semiconductors
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No Preview Available ! www.DataSheet4U.com MOTOROLA SEMICONDUCTOR TECHNICAL DATA Technical Summary 16-Bit Microcontroller Order this document by MC68HC16Z1TS/D Rev. 3 MC68HC16Z1 1 Introduction The MC68HC16Z1 is a high-speed 16-bit control unit that is upwardly code compatible with M68HC11 controllers. It is a member of the M68300/68HC16 Family of modular microcontrollers. M68HC16 controllers are built up from standard modules that interface through a common internal bus. Standardization facilitates rapid development of devices tailored for specific applications. The MC68HC16Z1 incorporates a true 16-bit central processing unit (CPU16), a system integration module (SIM), an 8/10-bit analog-to-digital converter (ADC), a queued serial module (QSM), a general- purpose timer (GPT), and a 2048-byte standby RAM (SRAM). These modules are interconnected by the intermodule bus (IMB). Maximum system clock for the MC68HC16Z1 is 16.78 MHz. A phase-locked loop circuit synthesizes the clock from a frequency reference. Either a crystal (nominal frequency: 32.768 kHz) or an externally generated signal can be used. System hardware and software support changes in clock rate during op- eration. Because the MC68HC16Z1 is a fully static design, register and memory contents are not affect- ed by clock rate changes. High-density complementary metal-oxideDsaetamSihcoenedt4uUct.ocor m(HCMOS) architecture makes the basic power consumption of the MC68HC16Z1 low. Power consumption can be minimized by stopping the system clock. The M68HC16 instruction set includes a low-power stop (LPSTOP) command that efficiently im- plements this capability. DataShee This document contains information on a new product. Specifications and information herein are subject to change without notice. DataSheet4U.com M © MOTOROLA INC., 1992, 1996 DataSheet4 U .com 1 page www.DataSheet4U.com PQS7/TXD PQS6/PCS3 PQS5/PCS2 PQS4/PCS1 PQS3/SS/PCS0 PQS2/SCK PQS1/MOSI PQS0/MISO et4U.com PAI PGP7/IC4/OC5/OC1 PGP6/OC4/OC1 PGP5/OC3/OC1 PGP4/OC2/OC1 PGP3/OC1 PGP2/IC3 PGP1/IC2 PGP0/IC1 PWMA PWMB PCLK VDD VSS PADA7/AN7 PADA6/AN6 PADA5/AN5 PADA4/AN4 PADA3/AN3 PADA2/AN2 PADA1/AN1 PADA0/AN0 VRH VRL VDDA VSSA VSTBY BKPT/DSCLK IPIPE1/DSI IPIPE0/DSO GPT PAI IC4/OC5/OC1 OC4/OC1 OC3/OC1 OC2/OC1 OC1 IC3 IC2 IC1 PWMA PWMB PCLK TXD PCS3 PCS2 PCS1 PCS0 SCK MOSI MISO QSM IMB DataSheet4U.com CHIP SELECTS CS[10:0] BR BG BGACK FC2 FC1 FC0 SIM ADDR[23:0] EBI SIZ1 SIZ0 AS DS PE3 AVEC DSACK1 DSACK0 DATA[15:0] ADC SRAM CPU16 IRQ[7:1] VSTBY MODCLK CLOCK TSC TEST TSTME QUOT Figure 1 MC68HC16Z1 Block Diagram CSBOOT BR/CS0 BG/CS1 BGACK/CS2 ADDR23/CS10 PC6/ADDR22/CS9 PC5/ADDR21/CS8 PC4/ADDR20/CS7 PC3/ADDR19/CS6 PC2/FC2/CS5 PC1/FC1/CS4 PC0/FC0/CS3 ADDR[18:0] PE7/SIZ1 PE6/SIZ0 PE5/AS PE4/DS PE2/AVEC PE1/DSACK1 PE0/DSACK0 DATA[15:0] DataShee R/W RESET HALT BERR PF7/IRQ7 PF6/IRQ6 PF5/IRQ5 PF4/IRQ4 PF3/IRQ3 PF2/IRQ2 PF1/IRQ1 PF0/MODCLK CLKOUT XTAL EXTAL XFC VDDSYN TSTME/TSC FREEZE/QUOT Z1 BLOCK DataSheet4U.com MC68HC16Z1 MC68HC16Z1TS/D DataSheet4 U .com MOTOROLA 5 5 Page www.DataSheet4U.com Table 5 MC68HC16Z1 Signal Characteristics (Continued) Signal Name R/W RESET RXD SCK SIZ[1:0] SS TSC TSTME TXD VRH VRL XFC XTAL MCU Module SIM SIM QSM QSM SIM QSM SIM SIM QSM ADC ADC SIM SIM Signal Type Output Input/Output Input Input/Output Output Input Input Input Output Input Input Input Output Active State 1/0 0 — — — 0 — 0 — — — — — et4U.com Signal Name Address Strobe Autovector Bus Error Bus Grant Bus Grant Acknowledge Breakpoint Bus Request Chip Selects Boot Chip Select Address Bus Address Bus ADC Analog Input System Clockout Data Bus Data Strobe Halt Interrupt Request Level Data and Size Acknowledge Peripheral Chip Select Reset Test Mode Enable Development Serial In, Out, Clock Crystal Oscillator Function Codes DataSheet4U.com MC68HC16Z1 MC68HC16Z1TS/D DataSheet4 U .com Table 6 MC68HC16Z1 Signal Function Mnemonic Function AS Indicates that a valid address is on the address bus AVEC Requests an automatic vector during interrupt acknowledge BERR Indicates that a bus error has occurred BG Indicates that the MCU has relinquished the bus BGACK DatIanSdihcaeteets4tUha.ctoamn external device has assumed bus mastership BKPT Signals a hardware breakpoint to the CPU BR Indicates that an external device requires bus mastership CS[10:0] Select external devices at programmed addresses CSBOOT Chip select for external boot start-up ROM ADDR[19:0] 20-bit address bus used by CPU16 ADDR[23:20] 4 MSB on IMB, test only, outputs follow ADDR19 AN[7:0] Inputs to ADC MUX CLKOUT System clock output DATA[15:0] 16-bit data bus DS During a read cycle, indicates that an external device should place valid data on the data bus. During a write cycle, indicates that valid data is on the data bus HALT Suspend external bus activity IRQ[7:1] Provides an interrupt priority level to the CPU DSACK[1:0] Provide asynchronous data transfers and dynamic bus sizing PCS[3:0] QSPI peripheral chip selects RESET System reset TSTME Hardware enable for SIM test mode DSI, DSO, Serial I/O and clock for background debug mode DSCLK EXTAL, XTAL Connections for clock synthesizer circuit reference; a crystal or an external oscillator can be used FC[2:0] Identify processor state and current address space MOTOROLA 11 DataShee 11 Page

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