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PDF MMI4832 Data sheet ( Hoja de datos )
| Número de pieza | MMI4832 | |
| Descripción | Encoder Interface ic | |
| Fabricantes | MAZeT | |
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All information contained in this document is property of MAZeT
GmbH. No parts may be reproduced or copied, neither
electronically nor mechanically, except with explicit permission of
MAZeT GmbH. All mentioned company names and trade marks as
well as product names obey the rules of trade marks and intellectual
property.
NR.
1
VERSION UPDATE
EDITION
CONFIRMED
V 2.1
2003-04-17
Data Sheet
MMI 4832
Integrated Circuit for Position Measuring Systems Interfacing
Table of contents
1 INTRODUCTION
1.1 “EnDatâ“, “SSI“ transfer mode
1.2 “Incremental“ transfer mode:
1.3 Functions available in both transfer modes
1.4 Block diagram
2 PARALLEL INTERFACE
3 ENDATâ -INTERFACE
3.1 Transfer formats (EnDatâ)
3.2 Registers
4 INCREMENTAL INTERFACE DataSheet4U.com
4.1 Digital input filters
4.2 Edge evaluation
4.3 Counter
4.4 Preset register
4.5 Strobe register
4.6 Reference register
5 GENERAL-PURPOSE REGISTERS
5.1 Receive register
5.2 Multifunction register (MFR)
5.3 Control register
5.4 Status register
5.5 Interrupt mask
5.6 Timer
6 PIN DESCRIPTION
7 PACKAGE
8 GENERAL OPERATING CONDITIONS
9 TIME RELATIONSHIPS
1 µC PORT ADDRESSATION
1.1 Intel, no autoincrement
1.2 Intel, with autoincrement
1.3 Motorola, no autoincrement
1.4 Motorola, with autoincrement
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MAZeT GmbH Sales
Göschwitzer Straße 32
07745 JENA / GERMANY
DataSheet4U.comPhone: +49 3641 2809-0
Fax: +49 3641 2809-12
E-Mail: [email protected]
Url: http://www.MAZeT.de
Approvals
Compiled:
Checked:
Released:
Date
2002-04-30
2003-04-10
2003-04-17
Status: valid
MAZeT GmbH
DOC. NR.: DB-99-031e
Page 1 of 45
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DATA SHEET MMI4832
NR. EDITION
1 V 2.1
VERSION
CONFIRMED
2003/04/17
et4U.com
1.2 “Incremental“ transfer mode:
A direction discriminator uses the two 90°-square-wave signals (CHA, CHB) as input to generate
pulses which are then further processed in a downline 32-bit counter. This may be accomplished
with selectable single-, double- or quadruple-edge evaluation. CHC and CHD serve as index
tracks. Optionally, the MMI4832 may also be operated in pulse direction mode. For explanations
on how counting signals are generated and selected, you should refer to section 4.2. To reduce
the influence of interferences, programmable digital input filters can be selectively connected to
the four counter inputs CHA, CHB, CHC and CHD, the filter length being selectable in integer
multiples of the system clock.
The counter has a downline strobe register for the counter content to be written into this register
with a hardware strobe or a software strobe without any need to interrupt the counting process.
The counter is reset to zero if an index pulse is applied to any of the measuring system inputs
(CHA*CHB*CHC *CHD) with a concurrent software enable signal (control register bit (3), control
register bit (4)) or when the zero input is active (zero = low). /NIA is a low-active signal to serve as
the reset output of a counter circuit which functions as a master, in order to allow synchronization
of several measuring systems.
On selection of “Set-by-Reference” (control register bit (6)), an index pulse arriving at
(CHA*CHB*CHC*CHD) will cause the counter to be loaded with the preset register value. If
“Reset“ and “Set-by-Reference” are active at the same time, the “Reset” function will prevail.
On selection of “Reference Strobe” (control register bit (1)), the latest counter values at the
moment of an index pulse arriving at (CHA*CHB*CHC*CHD) will be loaded into the strobe
register.
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“Reference Compare“ (control register bit (2)) allows the current counter reading to be compared
with the value in the offset register. If the two values are found to be equal, status register bit (2)
will be set.
On selection of “Add Offset“, an offset is added to the incremental value. This function is enabled
by bit 10 of the control register. The full offset value (receive register + offset) is read from the
multifunction register address.
In “incremental“ transfer mode, the status register keeps track of reset, reference strobe, strobe
and interference events at the inputs of the measuring system.
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1.3 Functions available in both transfer modes
Acting in conjunction with the 8-bit status register and the 8-bit interrupt mask, the control register
supports easy recording and monitoring of the measured values.
The interrupt mask makes it possible to selectively trigger an interrupt request for messages from
a measuring system.
The two inputs /IR6 and /IR7 are recorded by the status register. They allow specific application
events (such as supply voltage availability, temperature, cable breakage, etc.) to be monitored.
In all three modes (EnDat, SSI, incremental), a timer for selection of a desired sampling repeat rate
(sampling rate) is available (compare with section 5.6). For a system clock rate of 24 MHz, the
selected sampling rate may be in the range of 0.417µs to 10.9 ms. Alternatively, measured values
can also be requested via the /STR input or a software strobe.
DataSheet4U.comAll information contained in this document relate to the technology available on date of
release and is preliminary. MAZeT GmbH reserves the right to technological changes
of devices and components described in this documentation.
DOC. NR:
DB-99-031e
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DATA SHEET MMI4832
NR. EDITION
1 V 2.1
VERSION
CONFIRMED
2003/04/17
3.2.3.3 Receive mode 3
Tells measuring system to send test values
M(2:0) = 2/h
The number of required transfer clocks is automatically generated. The test data word to be
received has a width of forty bits. Sending begins with the MSB. Once the LSB has been received,
the CRC hardware is enabled to receive a CRC code.
3.2.3.4 CRC
In each of the three receive modes described before, the CRC bits are compared with those CRC
bits which have been generated from the data stream that was received. On completion of a CRC
test, the serial-to-parallel converter is again operational.
3.2.3.5 Data loading into the receive register
A value received from the SPC is loaded into the receive register on completion of a serial-to-
parallel conversion process and completion of a CRC check, unless an error bit (compare with
status register) was set. A new and valid will only overwrite a previous value if the status bit 0 was
reset (read status register with reset).
(compare with section: 5.1.1.1)
* CRC test hardware according to EnDatâ definition V2.1 Appendix A4 of DR.J.HEIDENHAIN GmbH
4 Incremental Interface
4.1 Digital input filters
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Programmable digital filters are provided for the four input signals CHA, CHD, CHC, CHD to allow
interferences to be removed. For a signal to be identified as a useful signal, it must have a certain
minimum duration. If a signal fails to last for this minimum prescribed time, it will be detected as an
interference.
Filter programming, i.e. definition of the minimum required duration for a signal to qualify as “useful
signal“ is made via the control register bits (15:11).
Preselection of value [WTusable] for a desired minimum useful signal duration [Tusable]
[WTusable] = (Tnutz / 2*Tsys) – 1or
[WTusable] = (fsys / 2*fusable) - 1
Tusable - is the minimum duration of a useful signal
fusable - is the maximum frequency of a useful signal
fsys - is the system clock rate
Tsys - is the period of a system clock
Example:
In order to detect only signals with a frequency £ 312.5 kHz as useful input signals if a system clock of 20 MHz was set,
1F/h must be written into the control register bits (15:11) for WTusable.
Following a reset, the filters are turned off as a standard measure. On defining a value of 0/dec for
the control register bits (15:11), the filter will also be turned off.
DataSheet4U.comAll information contained in this document relate to the technology available on date of
release and is preliminary. MAZeT GmbH reserves the right to technological changes
of devices and components described in this documentation.
DOC. NR:
DB-99-031e
DataSheet4 U .com
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