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PDF VG26V18165D Data sheet ( Hoja de datos )
| Número de pieza | VG26V18165D | |
| Descripción | CMOS DRAM | |
| Fabricantes | Vanguard Microelectronics Limited | |
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VIS
VG26(V)(S)18165C/VG26(V)(S)18165D
1,048,576 x 16 - Bit
CMOS Dynamic RAM
Description
The device CMOS Dynamic RAM organized as 1,048,576 words x 16 bits with extended data out access mode. It is
fabricated with an advanced submicron CMOS technology and designed to operate from a single 5V only or 3.3V only
power supply. Low voltage operation is more suitable to be used on battery backup, portable electronic application. Self-
refresh is supported and CBR cycles are being performed. lt is packaged in JEDEC standard 42-pin 400mil SOJ and
50(44)-pin 400mil TSOPII.
Features
• Single 5V or 3.3V only power supply
• High speed tRAC access time: 50/60ns
• Extended-data-out (EDO) page mode access
• I/O level: TTL compatible (Vcc = 5V)
LVTTL compatible (Vcc = 3.3V)
• 4 refresh modes:
- RAS only refresh
- CAS - before - RAS refresh
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- Hidden refresh
- Self-refresh
• Refresh interval:
- RAS only refresh, CAS - before - RAS refresh and hidden refresh: 1024 cycles in 16 ms
- Self-refresh: 1024 cycles
• JEDEC standard pinout: 44-pin 400mil SOJ and 50(44)-pin 400mil TSOPII
DataShee
DataSheet4U.com
Document:1G5-0179
DataSheet4 U .com
Rev.2
Page 1
1 page  
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VIS
Absolute Maximum Ratings
Parameter
Voltage on an any pin relative to Vss
Supply voltage relative to Vss
Short circuit output current
Power dissipation
Operating temperature
Storage temperature
5V
3.3V
5V
3.3V
Symbol
VT
VCC
IOUT
PD
TOPT
TSTG
VG26(V)(S)18165C/VG26(V)(S)18165D
1,048,576 x 16 - Bit
CMOS Dynamic RAM
Value
-1.0 to + 7.0
-0.5 to + 4.6
-1.0 to + 7.0
-0.5 to + 4.6
50
1.0
0 to + 70
-55 to + 125
Unit
V
V
mA
W
°C
°C
Recommended DC Operating Conditions
Parameter/Condition
Sym-
bol
5 Volt Version
Min Typ Max
Supply Voltage
VCC 4.5 5.0 5.5
Input High Voltage, all inputs VIH
2.4
- VCC + 1.0
Input Low Voltage, all inputs VIL
-1.0
-
0.8
et4U.com
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3.3 Volt Version
Unit
Min Typ Max
3.15 3.3
3.6 V
2.0 - VCC + 0.3 V
-0.3 -
0.8 V
Capacitance
Ta = 25°C, VCC = 5V ±10 % or 3.3V ±10 %, f = 1MHz
Parameter
Symbol
Input capacitance (Address)
CI1
Input capacitance (RAS , LCAS , UCAS, OE, WE)
CI2
Output capacitance (Data-in, Data-out)
CI/O
Note: 1. Capacitance measured with effective capacitance measuring method.
2. RAS, LCAS and UCAS = VIH to disable Dout.
Max
5
7
7
Unit Note
pF 1
pF 1
pF 1, 2
DataShee
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Document:1G5-0179
DataSheet4 U .com
Rev.2
Page 5
5 Page 
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VIS
VG26(V)(S)18165C/VG26(V)(S)18165D
1,048,576 x 16 - Bit
CMOS Dynamic RAM
Notes :
1. AC measurements assume tT = 1ns.
2. An initial pause of 100 µs is required after power up, and it followed by a minimum of eight
initialization cycles (RAS - only refresh cycle or CAS - before - RAS refresh cycle). If the internal
refresh counter is used, a minimun of eight CAS - before - RAS refresh cycles are required.
3. In delayed write or read-modify-write cycles, OE must disable output buffer prior to applying data to
the device.
4. All the VCC and VSS pins shall be supplied with the same voltages.
5. When both LCAS and UCAS go low at the same time, all 16-bits data are witten into the device. LCAS
and UCAS cannot be staggered within the same write/read cycles.
6. tRAS(min) = tRWD(min)+tRWL(min)+tT in read-modify-write cycle.
7. tCAS(min) = tCWD(min)+tCWL(min)+tT in read-modify-write cycle.
8. tASC(min), tRCS(min), tWCS(min), and tRPC are determined by the falling edge of CAS .
9. tRCD(max) is specified as a reference point only, and tRAC(max) can be met with the tRCD(max) limit.
Otherwise, tRAC is controlled exclusively by tCAC if tRCD is greater than the specified tRCD(max) limit.
10. tRAD(max) is specified as a reference point only, and tRAC(max) can be met with the tRAD(max) limit.
Otherwise, tRAC is controlled exclusively by tAA if tRAD is greater than the specified tRAD(max) limit.
11. tCRP, tCHR, tRCH, tCPA and tCPW are determined by the rising edge of CAS .
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12. VIH(min) and VIL(max) are reference levels for measuring timing or input signals. Therefore,
transition time is measured between VIH and VIL.
13. Assumes that tRCD ≤ tRCD(max) and tRADD≤attaRSAhDe(meta4xU)..IcfotRmCD or tRAD is greater than the maximum
recommended value shown in this table, tRAC exceeds the value shown.
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14. Assumes that tRCD ≥ tRCD(max) and tRAD ≤ tRAD (max).
15. Access time is determined by the maximum of tAA, tCAC, tCPA.
16. Assumes that tRCD ≤ tRCD (max) and tRAD ≥ tRAD (max).
17. Either tRCH or tRRH must be satisfied for a read cycle.
18. tOFF(max) and tOEZ(max) define the time at which the output achieves the open circuit condition (high
impedance). tOFF is determined by the later rising edge of RAS or CAS.
19. tWCS, tRWD, tCWD, and tAWD are not restrictive operating parameters. They are included in the data
sheet as electrical characteristics only. If tWCS ≥ tWCS (min), the cycle is an early write cycle and the
data out will remain open circuit (high impedance) throughout the entire cycle. If tRWD ≥ tRWD (min),
tCWD ≥ tCWD (min), tAWD ≥ tAWD (min) and tCPW ≥ tCPW (min), the cycle is a read-modify-write and
the data output will contain data read from the selected cell. If neither of the above sets of conditions
is satisfied, the condition of the data output (at access time) is indeterminate.
20. tCWL shall be satisfied by both LCAS and UCAS.
21. These parameters are referenced to LCAS or LCAS separately in an early write cycle and to WE
edge in a delayed write or a read-modify-write cycle.
22. tRASP defines RAS pulse width in EDO page mode cycles.
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Document:1G5-0179
DataShee4t U .com
Rev.2
Page 11
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