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PDF SH67P33 Data sheet ( Hoja de datos )
| Número de pieza | SH67P33 | |
| Descripción | OTP 4-Bit Micro Controller | |
| Fabricantes | Sino Wealth Microelectronic | |
| Logotipo |  |
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SH67P33
OTP 4-bit Micro-controller
Features
SH6610C-based single-chip 4-bit micro-controller
ROM: 1K X 16 bits OTP ROM
RAM: 48 X 4 bits RAM (Data Memory)
Operation voltage: 1.8V - 3.6V (Typical: 3.0V)
16 CMOS bi-directional I/O pins and 1 COMS input pin
4-level subroutine nesting (including interrupts)
One 8-bit auto re-loadable timer/counter
Warm-up timer for power-on reset
Powerful interrupt sources:
- Internal interrupt (Timer0).
- External interrupts: (rising edge).
PORTB & PORTC or PORTB, PORTC & PORTD (Code
Option)
Remote control programmable carrier synthesizer
Oscillator :(Code Option)
- External Ceramic Resonator/Crystal Oscillator:
400kHz - 4MHz
- Built-in RC Oscillator: 4MHz typical
Instruction cycle time:
- 4/455kHz (≈ 8.79µs) for 455kHz OSC clock
- 4/4MHz (= 1µs) for 4MHz OSC clock
Two low power operation modes: HALT and STOP
Built-in watchdog timer
OTP type/Code protection
20-pin DIP/TSSOP/SOP package
General Description
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core with
function,
system will stop oscillator and remain low power dissipation.
Pin Configuration
DataShee
GND
PORTD.0
PORTD.1
PORTE.0 /OSCI
PORTE.1 /OSCO
PORTD.2
PORTC.0
PORTC.1
PORTC.2
PORTC.3
1
2
3
4
5
6
7
8
9
10
20 VDD
19 REM
18 PORTA.3
17 PORTA.2
16 PORTA.1
15 PORTA.0
14 PORTB.3
13 PORTB.2
12 PORTB.1
11 PORTB.0
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SH67P33
3. RAM
Built-in RAM contains of general-purpose data memory and system register. Because of its static nature, the RAM can keep
data after the CPU enters STOP or HALT.
3.1. RAM Addressing
Data memory and system register can be accessed in one instruction by direct addressing. The following is the memory
allocation map:
System register and I/O: $00 - $1F
Data memory: $020 - $04F
3.2 Configuration of System Register:
System Register $00-$1F RAM Map:
et4U.com
Address
$00
$01
$02
$03
$04
$05
$06 - $07
$08
$09
$0A
$0B
$0C
$0D
$0E
$0F
$10
$11
$12
$13
Bit3
-
-
-
-
TL0.3
TH0.3
-
PA.3
PB.3
PC.3
-
-
-
TBR.3
INX.3
DPL.3
-
-
PPULL
$14 WDT
$15 LVR3
$16 PACR.3
$17 PBCR.3
$18 PCCR.3
$19 -
$1A -
$1B CFL3
$1C CFL7
$1D CFH3
$1E CFH7
$1F -
Bit2
IET0
IRQT0
TM0.2
-
TL0.2
TH0.2
-
PA.2
PB.2
PC.2
PD.2
-
-
TBR.2
INX.2
DPL.2
DPM.2
DPH.2
CPS2
-
LVR2
PACR.2
PBCR.2
PCCR.2
PDCR.2
-
CFL2
CFL6
CFH2
CFH6
-
Bit1
-
-
TM0.1
-
TL0.1
TH0.1
-
PA.1
PB.1
PC.1
PD.1
PE.1
-
TBR.1
INX.1
DPL.1
DPM.1
DPH.1
CPS1
-
LVR1
PACR.1
PBCR.1
PCCR.1
PDCR.1
PECR.1
CFL1
CFL5
CFH1
CFH5
-
Bit0 R/W
Remarks
IEP R/W Interrupt enable flags
IRQP R/W Interrupt request flags
TM0.0 R/W Timer0 Mode register (Prescaler)
- - Reserved
TL0.0 R/W Timer0 load/counter register low nibble
TH0.0 R/W Timer0 load/counter register high nibble
- - Reserved
PA.0 R/W PORTA
PB.0 R/W PORTB
PC.0 R/W PORTC
PD.0 R/W PORTD
PE.0DataSRh/eWet4UP.cOoRmTE
REMO
REM
W Bit0: REMO output data
R Bit0: REM pin output status
TBR.0 R/W Table Branch Register
INX.0 R/W Pseudo index register
DPL.0 R/W Data pointer for INX low nibble
DPM.0 R/W Data pointer for INX middle nibble
DPH.0 R/W Data pointer for INX high nibble
CPS0
-
LVR0
R/W
Bit2-0: Carrier count source pre-divider
Bit3: Port Pull-low MOS Control
R/W
Bit3: Watchdog timer reset/flag
(Write 1 to reset WDT timer)
LVR Enable Control (LVR3 - 0):
R/W 1010: LVR Disable
Else: LVR Enable (Power-on initial 0000)
PACR.0 R/W PORTA input/output control
PBCR.0 R/W PORTB input/output control
PCCR.0 R/W PORTC input/output control
0 R/W PORTD input/output control
PECR.0 R/W PORTE input/output control
CFL0 R/W Carrier low level timer load data register (low nibble)
CFL4 R/W Carrier low level timer load data register (high nibble)
CFH0 R/W Carrier high level timer load data register (low nibble)
CFH4 R/W Carrier high level timer load data register (high nibble)
- - Reserved
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CCC
PPP
SSS
210
SYSTEM
CLOCK
Pre-
scaler
divider
Low level timer load data
register
Carrier generating
counter
Carrier
output
REM
High level timer load data
register
CARRIER SYNTHESIZER
REMO
Figure 4. Remote Control Functional Block Diagram
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COUNTER
SOURCE
RESET
SIGNAL
REMO
COUNTER
OVERFLOW
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1:load high level data register
23
21
2:High level counter overflow and load lowlevel data register
2
3
23
3:Low level counter overflow and load high level data register
MODIFY
HIGH&LOW
DATA
REGISTER
CARRIER
OUTPUT
OUTPUT
OUTPUT
HIGH
HIGH
LEVEL OUTPUT LEVEL OUTPUT
LOW
LOW
LEVEL
LEVEL
n1Dec=($1E,$1D)Hex
n2Dec=($1C,$1B)Hex
(255-
n1)clock
interval
(255-
n2)clock
interval
carrier wave
period
REM
Figure 5. Carrier Synthesize Wave
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SH67P33
23
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| Páginas | Total 26 Páginas | |
| PDF Descargar | [ Datasheet SH67P33.PDF ] | |
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