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BH62UV8000 데이터시트 PDF




Brilliance Semiconductor에서 제조한 전자 부품 BH62UV8000은 전자 산업 및 응용 분야에서
광범위하게 사용되는 반도체 소자입니다.


 

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부품번호 BH62UV8000 기능
기능 Ultra Low Power/High Speed CMOS SRAM
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BH62UV8000 데이터시트, 핀배열, 회로
www.DataSheet4U.com
BSI Ultra Low Power/High Speed CMOS SRAM
1M X 8 bit
BH62UV8000
n FEATURES
Ÿ Wide VCC low operation voltage : 1.65V ~ 3.6V
Ÿ Ultra low power consumption :
VCC = 3.0V
Operation current : 5.0mA at 70ns at 25OC
1.5mA at 1MHz at 25OC
Standby current : 2.5uA at 25OC
VCC = 2.0V Data retention current : 2.5uA at 25OC
Ÿ High speed access time :
-70 70ns at 1.8V at 85OC
Ÿ Automatic power down when chip is deselected
Ÿ Easy expansion with CE1, CE2 and OE options
Ÿ Three state outputs and TTL compatible
Ÿ Fully static operation, no clock, no refreash
Ÿ Data retention supply voltage as low as 1.0V
n DESCRIPTION
The BH62UV8000 is a high performance, ultra low power CMOS Static
Random Access Memory organized as 1,048,576 by 8 bits and
operates in a wide range of 1.65V to 3.6V supply voltage.
Advanced CMOS technology and circuit techniques provide both high
speed and low power features with typical operating current of 1.5mA at
1MHz at 3.6V/25OC and maximum access time of 70ns at 1.8V/85OC.
Easy memory expansion is provided by an active LOW chip enable
(CE1), an active HIGH chip enable (CE2) and active LOW output
enable (OE) and three-state output drivers.
The BH62UV8000 has an automatic power down feature, reducing the
power consumption significantly when chip is deselected.
The BH62UV8000 is available in DICE form and 48-ball BGA package.
n PRODUCT FAMILY
PRODUCT
FAMILY
OPERATING
TEMPERATURE
VCC
RANGE
SPEED
(ns)
VCC=1.8~3.6V
POWER CONSUMPTION
STANDBY
(ICCSB1, Max)
Operating
(ICC, Max)
VCC=3.6V VCC=1.8V VCC=3.6V VCC=1.8V
PKG TYPE
BH62UV8000AI
BH62UV8000DI
+0OC to +70OC
-25OC to +85OC
n PIN CONFIGURATIONS
1.65V ~ 3.6V
70 13uA 10uA 10mA 7mA
BGA-48-0608
DICE
70 15uA 12uA 10mA 7mA
DataSheet4U.com
n BLOCK DIAGRAM
DataShee
123456
A NC OE A0 A1 A2 CE2
B NC NC A3 A4 CE1 NC
C DQ0 NC A5 A6 NC D04
D VSS DQ1 A17 A7 DQ5 VCC
E VCC DQ2 VSS A16 DQ6 VSS
F D3 NC A14 A15 NC DQ7
G NC NC A12 A13 WE NC
H
A18 A8
A9 A10 A11 A19
48-ball BGA top view
A12
A11
A10
A9
A8
A7
A6
A5
A4
A3
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
CE1
CE2
WE
OE
VCC
GND
Address
Input
Buffer
10
Row
Decoder
1024
Memory Array
1024 x 18192
8
8
Control
Data
Input
Buffer
Data
Output
Buffer
8
8
8192
Column I/O
Write Driver
Sense Amp
1024
Column Decoder
10
Address Input Buffer
A19 A18 A17 A15 A14 A13 A16 A2 A1 A0
Brilliance Semiconductor, Inc. reserves the right to modify document contents without notice.
Detailed product characteristic test report is available upon request and being accepted.
DataSheet4U.com
R0201-BH62UV8000
1
Revision 1.0
Jul. 2005
DataSheet4 U .com




BH62UV8000 pdf, 반도체, 판매, 대치품
www.DataSheet4U.com
BSI
n LOW VCC DATA RETENTION WAVEFORM (2) (CE2 Controlled)
VCC
VCC
tCDR
Data Retention Mode
VDR1.0V
CE2
CE20.2V
VIL
BH62UV8000
VCC
tR
VIL
n AC TEST CONDITIONS
(Test Load and Input/Output Reference)
n KEY TO SWITCHING WAVEFORMS
Input Pulse Levels
Input Rise and Fall Times
Input and Output Timing
Reference Level
Output Load
tCLZ1, tCLZ2, tOLZ, tCHZ1,
tCHZ2, tOHZ, tWHZ, tOW
Others
VCC / 0V
1V/ns
0.5Vcc
CL = 5pF+1TTL
CL = 30pF+1TTL
WAVEFORM
ALL INPUT PULSES
1 TTL
VCC
90% 90%
Output
CL(1)
GND
10%
→←
Rise Time:
et4U.com
1V/ns
1. Including jig and scope capacitance.
10%
→←
Fall Time:
1V/ns
DataSheet4U.com
INPUTS
MUST BE
STEADY
MAY CHANGE
FROM HTO L
MAY CHANGE
FROM LTO H
DONT CARE
ANY CHANGE
PERMITTED
DOES NOT
APPLY
OUTPUTS
MUST BE
STEADY
WILL BE CHANGE
FROM HTO L
WILL BE CHANGE
FROM LTO H
CHANGE :
STATE UNKNOW
CENTER LINE IS
HIGH INPEDANCE
OFFSTATE
n AC ELECTRICAL CHARACTERISTICS (TA = -25OC to +85OC)
READ CYCLE
JEDEC
PARAMETER
NAME
tAVAX
tAVQX
tE1LQV
tE2LQV
tGLQV
tE1LQX
tE2LQX
tGLQX
tE1HQZ
tE2HQZ
tGHQZ
tAVQX
PARANETER
NAME
tRC
tAA
tACS1
tACS2
tOE
tCLZ1
tCLZ2
tOLZ
tCHZ1
tCHZ2
tOHZ
tOH
DESCRIPTION
Read Cycle Time
Address Access Time
Chip Select Access Time
Chip Select Access Time
Output Enable to Output Valid
Chip Select to Output Low Z
Chip Select to Output Low Z
Output Enable to Output Low Z
Chip Select to Output High Z
Chip Select to Output High Z
Output Enable to Output High Z
Data Hold from Address Change
(CE1)
(CE2)
(CE1)
(CE2)
(CE1)
(CE2)
CYCLE TIME : 70ns
MIN.
TYP.
MAX.
70 --
--
-- -- 70
-- -- 70
-- -- 70
-- -- 30
10 --
--
10 --
--
5 -- --
-- -- 25
-- -- 25
-- -- 25
10 --
--
UNITS
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
DataShee
DataSheet4U.com
R0201-BH62UV8000
DataSheet4 U .com
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BH62UV8000 전자부품, 판매, 대치품
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BSI
WRITE CYCLE 2 (1,6)
ADDRESS
CE1
tWC
tCW(11)
(5)
BH62UV8000
et4U.com
CE2
WE
DOUT
DIN
(5)
tAW tCW(11)
tWP(2)
tAS
tWHZ(4,10)
tWR2(3)
tOW
(7)
tDW
tDH (8,9)
DataSheet4U.com
NOTES:
1. WE must be high during address transitions.
2. The internal write time of the memory is defined by the overlap of CE1 and CE2 active and WE low.
All signals must be active to initiate a write and any one signal can terminate a write by going inactive.
The data input setup and hold timing should be referenced to the second transition edge of the signal
that terminates the write.
3. tWR is measured from the earlier of CE1 or WE going high or CE2 going low at the end of write cycle.
4. During this period, DQ pins are in the output state so that the input signals of opposite phase to the
outputs must not be applied.
5. If the CE1 low transition or the CE2 high transition occurs simultaneously with the WE low transitions
or after the WE transition, output remain in a high impedance state.
6. OE is continuously low (OE = VIL).
7. DOUT is the same phase of write data of this write cycle.
8. DOUT is the read data of next address.
9. If CE1 is low and CE2 is high during this period, DQ pins are in the output state. Then the data input
signals of opposite phase to the outputs must not be applied to them.
10.Transition is measured ± 500mV from steady state with CL = 5pF.
The parameter is guaranteed but not 100% tested.
11.tCW is measured from the later of CE1 going low or CE2 going high to the end of write.
(8)
DataShee
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R0201-BH62UV8000
DataSheet4 U .com
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