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W78E051B PDF 데이터시트 : 부품 기능 및 핀배열

부품번호 W78E051B
기능 8-Bit Microcontroller
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W78E051B 데이터시트, 핀배열, 회로
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W78E51B Data Sheet
8-BIT MICROCONTROLLER
Table of Contents-
1. GENERAL DESCRIPTION ......................................................................................................... 3
2. FEATURES ................................................................................................................................. 3
3. PIN CONFIGURATIONS ............................................................................................................ 4
4. PIN DESCRIPTION..................................................................................................................... 5
5. BLOCK DIAGRAM ...................................................................................................................... 6
6. FUNCTIONAL DESCRIPTION ................................................................................................... 7
6.1 New Defined Peripheral.................................................................................................. 7
6.2 Reduce EMI Emission .................................................................................................... 8
6.3 Watchdog Timer ............................................................................................................. 9
6.4 Clock ............................................................................................................................. 10
6.5 Power Management...................................................................................................... 10
6.6 Reset............................................................................................................................. 11
6.7 On-Chip ROM Characteristics ...................................................................................... 11
6.7.1 Read Operation ..............................................................................................................11
6.7.2 Output Disable ConditDioant.a..S...h..e..e..t..4..U....c..o..m........................................................................11
6.7.3 Program Operation .........................................................................................................11
6.7.4 Program Verify Operation ...............................................................................................11
6.7.5 Erase Operation .............................................................................................................11
6.7.6 Erase Verify Operation ...................................................................................................11
6.7.7 Program/Erase Inhibit Operation ....................................................................................12
7. SECURITY BITS ....................................................................................................................... 12
7.1 Lock Bit ......................................................................................................................... 13
7.2 MOVC Inhibit................................................................................................................. 13
7.3 Encryption ..................................................................................................................... 13
8. ELECREICAL CHARACTERISTICS......................................................................................... 14
8.1 Absolute Maximum Ratings .......................................................................................... 14
8.2 D.C. Characteristics...................................................................................................... 14
8.3 A.C. Characteristics ...................................................................................................... 15
8.3.1 Clock Input Waveform ....................................................................................................16
8.3.2 Program Fetch Cycle......................................................................................................16
8.3.3 Data Read Cycle ............................................................................................................16
8.3.4 Data Write Cycle.............................................................................................................17
8.3.5 Port Access Cycle ..........................................................................................................17
8.3.6 Program Operation .........................................................................................................17
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Publication Release Date: Sep. 6, 2005
- 1 - Revision A7
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3. PIN CONFIGURATIONS
40-Pin DIP (W78E51B)
P1.0
P1.1
P1.2
P1.3
P1.4
P1.5
P1.6
P1.7
RST
RXD, P3.0
TXD, P3.1
INT0, P3.2
INT1, P3.3
T0, P3.4
T1, P3.5
WR, P3.6
RD, P3.7
XTAL2
XTAL1
VSS
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
40 VDD
39 P0.0, AD0
38 P0.1, AD1
37 P0.2, AD2
36 P0.3, AD3
35 P0.4, AD4
34 P0.5, AD5
33 P0.6, AD6
32 P0.7, AD7
31 EA
30 ALE
29 PSEN
28 P2.7, A15
27 P2.6, A14
26 P2.5, A13
25 P2.4, A12
24 P2.3, A11
23 P2.2, A10
22 P2.1, A9
21 P2.0, A8
44-Pin PLCC (W78E51BP)
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44-Pin QFP (W78E51BF)
/
I
N AAAA
T DDDD
3 0123
, ,,,,
P P P PP P PP P P
1 1 1 11 4V 00 0 0
. . . . . . D. . . .
4 3 2 10 2D01 2 3
P1.5
P1.6
P1.7
RST
RXD, P3.0
INT2, P4.3
TXD, P3.1
INT0, P3.2
INT1, P3.3
T0, P3.4
T1, P3.5
6 5 4 3 2 1 44 43 42 41 40
7 39
8 38
9 37
10 36
11 35
12 34
13 33
14 32
15 31
16 30
17 29
18 19 20 21 22 23 24 25 26 27 28
PP XXVPPP P P P
33 TTS4 22 2 2 2
. . AAS. . . . . .
67 LL 001 2 3 4
, , 21
,, , , ,
/ / AA A A A
WR
89 1 1 1
RD
012
P0.4, AD4
P0.5, AD5
P0.6, AD6
P0.7, AD7
EA
P4.1
ALE
PSEN
P2.7, A15
P2.6, A14
P2.5, A13
/
I
N AAAA
T DDDD
3 0123
, ,,,,
P P P PP P PP P P
1 1 1 11 4V 00 0 0
. . . . . . D. . . .
4 3 2 10 2D 01 2 3
P1.5
P1.6
P1.7
RST
RXD, P3.0
INT2, P4.3
TXD, P3.1
INT0, P3.2
INT1, P3.3
T0, P3.4
T1, P3.5
44 43 42 41 40 39 38 37 36 35 34
1 33
2 32
3 31
4 30
5 29
6 28
7 27
8 26
9 25
10 24
11 23
12 13 14 15 16 17 18 19 20 21 22
PP X X V PPP P P P
33 TTS422 2 2 2
. . AAS. . . . . .
67 L L 001 2 3 4
, , 21
,, , , ,
/ / AA A A A
WR
89 1 1 1
RD
0 12
P0.4, AD4
P0.5, AD5
P0.6, AD6
P0.7, AD7
EA
P4.1
ALE
PSEN
P2.7, A15
P2.6, A14
P2.5, A13
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6. FUNCTIONAL DESCRIPTION
The W78E51B architecture consists of a core controller surrounded by various registers, five general
purpose I/O ports, 128 bytes of RAM, two timer/counters, and a serial port. The processor supports
111 different opcodes and references both a 64K program address space and a 64K data storage
space.
6.1 New Defined Peripheral
In order to be more suitable for I/O, an extra 4-bit bit-addressable port P4 and two external interrupt
INT2 , INT3 has been added to either the PLCC or QFP 44 pin package. And description follows:
INT2 / INT3
Two additional external interrupts, INT2 and INT3 , whose functions are similar to those of external
interrupt 0 and 1 in the standard 80C52. The functions/status of these interrupts are
determined/shown by the bits in the XICON (External Interrupt Control) register. The XICON register is
bit-addressable but is not a standard register in the standard 80C52. Its address is at 0C0H. To
set/clear bits in the XICON register, one can use the "SETB (/CLR) bit" instruction. For example,
"SETB 0C2H" sets the EX2 bit of XICON.
XICON - external interrupt control (C0H)
PX3 EX3
IE3
IT3 PX2 EX2 IE2
IT2
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PX3: External interrupt 3 priority high if set
EX3: External interrupt 3 enable if set
IE3: If IT3 = 1, IE3 is set/cleared automatically by hardware when interrupt is detected/serviced
IT3: External interrupt 3 is falling-edge/low-level triggered when this bit is set/cleared by software
PX2: External interrupt 2 priority high if set
EX2: External interrupt 2 enable if set
IE2: If IT2 = 1, IE2 is set/cleared automatically by hardware when interrupt is detected/serviced
IT2: External interrupt 2 is falling-edge/low-level triggered when this bit is set/cleared by software
Seven-source interrupt information
INTERRUPT SOURCE
External Interrupt 0
Timer/Counter 0
External Interrupt 1
Timer/Counter 1
Serial Port
External Interrupt 2
External Interrupt 3
VECTOR
ADDRESS
03H
0BH
13H
1BH
23H
33H
3BH
POLLING SEQUENCE
WITHIN PRIORITY
LEVEL
0 (highest)
1
2
3
4
5
6 (lowest)
ENABLE
REQUIRED
SETTINGS
IE.0
IE.1
IE.2
IE.3
IE.4
XICON.2
XICON.6
INTERRUPT TYPE
EDGE/LEVEL
TCON.0
-
TCON.2
-
-
XICON.0
XICON.3
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Publication Release Date: Sep. 6, 2005
- 7 - Revision A7

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