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PDF LXT332 Data sheet ( Hoja de datos )
| Número de pieza | LXT332 | |
| Descripción | Dual T1/E1 Line Interface Unit with Crystal-less Attenuation | |
| Fabricantes | Level One | |
| Logotipo |  |
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Hay una vista previa y un enlace de descarga de LXT332 (archivo pdf) en la parte inferior de esta página. Total 30 Páginas | ||
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TCLK
TPOS
TNEG
JASEL
RNEG
RPOS
RCLK
LOS
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QRSS / BPV Generator
B8ZS/HDB3
Unipolar
Encoder
Encoder
Enable
RLOOP
Enable
Decoder Remote
Enable Loopback
B8ZS/HDB3
Unipolar
Decoder
Jitter
Attenuator
Transmit
Timing &
Control
TAOS
Enable
Serial Word
Equalizer
Monitor
LEN Select
DFM
Local
Loopback
LLOOP
Enable
Internal
Clock
Generator
Data Slicers
Timing and
Data
Recovery
Line Drivers
Serial
Port
Peak
Detector
QRSS Detector
LOS
Processor
LOS/Clear
Transceiver 0
Transceiver 1
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TTIP
TRING
DFM
INT0/1
PS0/1
CLKE
SCLK
SDI
SDO
MCLK
HFC
RTIP
RRING
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éì ê TPOS0 DI Transmit Positive and Negative Data - Port 0. In the Bipolar I/O mode,
(Bipolar)
these pins are the positive and negative sides of a bipolar input pair for port
éë
é
TNEG0
0. Data to be transmitted onto the twisted-pair line is input at these pins.
DI However, when the TRSTE pin is clocked by MCLK, the LXT332 switches
(Bipolar)
to a unipolar mode. Table 2 describes Unipolar mode pin functions.
éê è RNEG0 DO Receive Positive and Negative Data - Port 0. In the Bipolar I/O mode,
(Bipolar)
these pins are the data outputs from port 0. A signal on RNEG corresponds
éé
ç
RPOS0
to receipt of a negative pulse on RTIP/RRING. A signal on RPOS corre-
DO sponds to receipt of a positive pulse on RTIP/RRING. RNEG/RPOS outputs
(Bipolar)
are Non-Return-to-Zero (NRZ). In Host mode, CLKE determines the clock
edge at which these outputs are stable and valid.
ì æ RCLK0 DO Receive Clock - Port 0. This clock is recovered from the input signal.
Under Loss of Signal (LOS) conditions, this output is derived from MCLK.
ë å SCLK DI Serial Clock. The Serial Clock shifts data into or out from the serial inter-
face register of the selected port.
ê ä VCQ0 DI/O Provides Violation insert, High Frequency Clock, or QRSS generation/detec-
tion functions for Port 0. Pin operation is determined by the VCQE pin.
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Violation Insertion Function. When the Violation insertion function is
enabled, this pin is sampled on the falling edge of TCLK to control bipolar
violation (BPV) insertion. If High, a BPV is inserted at the next available
mark transmitted from port 0. A Low-to-High transition is required for each
subsDeqautaenSthveioelta4tiUo.ncionmsertion. (B8ZS and HDB3 zero suppression codes are
not violated.)
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Clock Function. When the Clock function is enabled, this pin outputs a
High Frequency Clock (12.352 MHz for T1, 16.384 MHz for E1) tied to the
jitter attenuated clock of port 0. If no JA clock is available, HFC is locked to
the 8x receive timing recovery clock.
Quasi Random Signal Source (QRSS) Function. When the QRSS function
is enabled, a High on this pin enables the QRSS detection circuit and causes
the LXT332 to transmit the QRSS pattern onto the twisted-pair line from
port 0. For error-free QRSS transmission, TPOS0 must be held Low. To
insert errors into the pattern, TPOS must transition from Low to High (TPOS
is sampled on the falling edge of MCLK). A Low-to-High transition is
required for each subsequent violation insertion. (B8ZS and HDB3 zero
suppression codes are not violated.)
é ìí INT1 DO Interrupt Outputs. The interrupt outputs go Low to flag the host processor
è ìì INT0 DO that the respective port has changed state. INT0 and INT1 are open drain
outputs. Each must be tied to VCC through a resistor.
ç ìë MCLK DI Master Clock. The master clock (1.544 MHz for T1, 2.048 MHz for E1)
input must be independent, free-running, continuously active and jitter free
for receiver operation. Since the transceivers derive their RCLK timing from
the MCLK input on Loss of Signal (LOS), MCLK cannot be derived from
RCLK.
æ
ìê
GND
– Ground. Ground return for power supply VCC.
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41 3 TDATA0 DI Transmit Data - Port 0. In the Unipolar mode, the data to be transmitted
onto the line from port 0 is input at this pin.
42 4 ECE0 DI Encoder Enable - Port 0. In the Unipolar mode, a High on this pin enables
the B8ZS or HDB3 encoder and decoder for port 0.
43 5 BPV0 DO Bipolar Violation - Port 0. In the Unipolar mode this indicator output goes
High when a bipolar violation is received at port 0.
44 6 RDATA0 DO Receive Data - Port 0. In the Unipolar mode, RDATA is a Non-Return-to-
Zero (NRZ) output. RDATA is stable and valid on the rising edge of
RCLK.
34 40 RDATA1 DO Receive Data - Port 1. In the Unipolar mode, RDATA is a Non-Return-to-
Zero (NRZ) output. RDATA is stable and valid on the rising edge of
RCLK.
35 41 BPV1 DO Bipolar Violation - Port 1. In the Unipolar mode this indicator output goes
High when a bipolar violation is received at port 1.
36 42 ECE1 DI Encoder Enable - Port 1. In the Unipolar mode, a High on this pin enables
the B8ZS or HDB3 encoder and decoder for port 1.
37 43 TDATA1 DI Transmit Data - Port 1. In the Unipolar mode, the data to be transmitted
onto the line from port 1 is input at this pin.
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11 Page | ||
| Páginas | Total 30 Páginas | |
| PDF Descargar | [ Datasheet LXT332.PDF ] | |
Hoja de datos destacado
| Número de pieza | Descripción | Fabricantes |
| LXT331 | Dual T1/E1 Line Interface Unit | Level One |
| LXT332 | Dual T1/E1 Line Interface Unit |  Intel |
| LXT332 | Dual T1/E1 Line Interface Unit with Crystal-less Attenuation | Level One |
| LXT334 | Quad Short Haul Transceiver | Intel |
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