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EK7606 PDF 데이터시트 : 부품 기능 및 핀배열

부품번호 EK7606
기능 240 Output Analog Source Driver For av Application Cof / Cog
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EK7606 데이터시트, 핀배열, 회로
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EK7606C PRELIMINARY DATA SHEETʳ
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CONFIDENTIAL




EK7606 pdf, 반도체, 판매, 대치품
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EUREKA
EK7606C
240- Output TFT LCD Analog Source Driver
1. GENERAL DESCRIPTION
The EK7606C is an analog, fully color, source driver for TFT LCD panels designed for camera, TV etc.
Analog R, G and B signal are applied directly on the chip. For each of the 240 outputs, the voltage is
sampled and buffered to the panel. With a double sample and hold circuit a new voltage can be
sample whereas the previous sample voltage is applied to the panel.
According to different modes, the 3 input voltages (VA, VB, VC) can be applied on different output to
support various pixel array types.
The 3 input voltages (VA, VB, VC) can be sampled simultaneously or sequentially to have a better
flexibility with the input voltage. Using enable signal (STHx), several chips can be cascaded for large
panel.
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2. FEATURES
z LCD outputs: 240
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z Bi-directional shift ( L/R )
z Simultaneous or Sequential RGB acquisition mode
z X1 or X3 clock mode
z High frequency Sampling 10MHz (x1)
z Automatic low power consumption mode after data capture (gated clock)
z RGB color selection (automatic or manual)
z Logic power supply voltage VDD: 2.7V – 5.25V
z LCD power supply voltage AVDD: 4.5V – 5.5V
z Output dynamic range AVSS+0.2V to AVDD-0.2V
z Applicable to COF/COG
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July 2003
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CONFIDENTIAL3 Preliminary Rev. 0.1

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EK7606 전자부품, 판매, 대치품
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EUREKA
EK7606C
5. PIN FUNCTION DESCRIPTION
Table 1. Pin function description
Signal Name Pin Type
Function
Qa1 to Qa80 Output
Liquid-crystal application voltages
Qb1 to Qb80
Each QaX, QbX or QcX correspond to one of the analog
Qc1 to Qc80
sample input signal VA, VB or VC.
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VA
VB
VC
L/R
STH1
STH2
CPH1
CPH2
CPH3
INH
July 2003
Input
Video input signal
Analog video input signal that is sampled internally and applied
to the panel.
Input
Bidir
Controls the display data shift direction
L/R = H : STH1 input, Qa1oQc80, STH2 output.
L/R = L : STH2 input, Qc80oQa1, STH1 output.
Right shift start pulse
L/R = H : Becomes the start pulse input pin.
Bidir
L/R = L : Becomes the start pulse output pin.
Left shift start pulse
L/R = H : Becomes the start pulse output pin.
Input
(Pull-down
CPH2 & CPH3
@ TEST2 = L
And MODE=H)
Input
L/R = L : Becomes the start pulse input pin.
Sampling clock input
Refers to the analog data-sampling clock. The sampling starts
at the first rising edge of CPH1 when STH1 ( L/R =H) is
activated.
CPH1 canDbaetaiSnhteerenta4llUy .dcoivmided (x3 mode) to generate internal
clock signal CPH1’.
The sampling can be simultaneous or sequential.
In simultaneous mode, the sampling is made during CPH1
(CPH1’) period for all output.
In sequential mode, the sampling is made according the table
below :
CPH1 (CPH1’) control the sampling for Qa1oQa80
CPH2 (CPH2’) control the sampling for Qb1oQb80
CPH3 (CPH3)’ control the sampling for Qc1oQc80
When clock mode x1 and sequential is selected, the three
inputs CPH1, CPH2 and CPH3 must have an input clock signal
applied. Otherwise only CPH1 must have input clock applied.
Load line
The sampled voltages are connecting to the panel at the rising
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edge of INH . The outputs of SHA(B) that was in sample mode
are applied to the panel, whereas the SHB(A) becomes ready
to sample new values.
During INH = L, output level is HiZ state and this signal
initialise the internal circuits.
-6-
CONFIDENTIALPreliminary Rev. 0.1
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