|
|
PDF COPC912CH Data sheet ( Hoja de datos )
| Número de pieza | COPC912CH | |
| Descripción | 8-Bit Microcontroller | |
| Fabricantes | National Semiconductor | |
| Logotipo |  |
|
Hay una vista previa y un enlace de descarga de COPC912CH (archivo pdf) en la parte inferior de esta página. Total 24 Páginas | ||
|
No Preview Available !
www.DataSheet4U.com
August 1996
COP912C COP912CH 8-Bit Microcontroller
General Description
CPU Instruction Set Features
The COP912C COP912CH are members of the COP8TM
8-bit MicroController family They are fully static Microcon-
trollers fabricated using double-metal silicon gate micro-
CMOS technology These low cost MicroControllers are
complete microcomputers containing all system timing in-
terrupt logic ROM RAM and I O necessary to implement
dedicated control functions in a variety of applications Fea-
tures include an 8-bit memory mapped architecture
MICROWlRETM serial I O a 16-bit timer counter with cap-
ture register and a multi-sourced interrupt Each I O pin has
software selectable options to adapt the device to the spe-
cific application The device operates over voltage ranges
from 2 3V to 4 0V (COP912C) and from 4 0V to 5 5V
(COP912CH) High throughput is achieved with an efficient
regular instruction set operating at a minimum of 2 ms per
instruction rate
Key Features
Y Lowest cost COP8 microcontroller
Y 16-bit multi-function timer supporting
PWM mode
External event counter mode
Input capture mode
Y 768 bytes of ROM
Y 64 bytes of RAM
Y Instruction cycle time of 2 ms for COP912CH and
2 5 ms for COP912C
Y Three multi-sourced interrupts servicing
External Interrupt with selectable edge
Timer interrupt
Software interrupt
Y Versatile and easy to use instruction set
Y 8-bit Stack Pointer (SP) stack in RAM
Y Two 8-bit Register Indirect Memory Pointers (B X)
Fully Static CMOS
Y Low current drain (typically k 1 mA)
Y Single supply operation 2 3V to 4 0V or 4 0V to 5 5V
Y Temperature range 0 C to a70 C
Development Support
Y Emulation and OTP devices
Y Real time emulation and full program debug offered by
MetaLink Development System
Applications
Y Electronic keys and switches
Y Remote Control
I O Features
Y Timers
Y Alarms
Y Memory mapped I O
Y Small industrial control units
Y
Software
Push-Pull
Input)
selectable I O
Output Weak
Poupllt-iUonpsIn(TpuRtI-SHTigAhTEImpeOduatDpnucaet taSYYhLTeoeewmtp4ceoUrsat.tucsrloeavmme ectoenrstrollers
Y Schmitt trigger inputs on Port G
Y Small domestic appliances
Y MICROWIRE PLUSTM Serial I O
Y Toys and games
Y Packages 20 DIP SO with 16 I O pins
Block Diagram
DataShee
TRI-STATE is a registered trademark of National Semiconductor Corporation
COP8TM MICROWIRE PLUSTM WATCHDOGTM and MICROWIRETM are trademarks of National Semiconductor Corporation
PC is a registered trademark of International Business Machines Corp
iceMasterTM is a trademark of MetaLink Corporation
C1996 National Semiconductor Corporation TL DD12060
RRD-B30M96 Printed in U S A
TL DD 12060 – 1
http www national com
DataSheet4U.com
DataSheet4 U .com
1 page  
www.DataSheet4U.com
et4U.com
Pin Description
VCC and GND are the power supply pins
CKI is the clock input This can come from an external
source a R C generated oscillator or a crystal (in conjunc-
tion with CKO) See Oscillator description
RESET is the master reset input See Reset description
PORT L is an 8-bit I O port
There are two registers associated to configure the L port a
data register and a configuration register Therefore each L
I O bit can be individually configured under software control
as shown below
The selection of alternate Port G functions are done through
registers PSW 00EF to enable external interrupt and
CNTRL 00EE to select TIO and MICROWIRE operations
Functional Description
The internal architecture is shown in the block diagram
Data paths are illustrated in simplified form to depict how
the various logic elements communicate with each other in
implementing the instruction set of the device
ALU AND CPU REGISTERS
Port L Config Port L Data
PORT L
Setup
The ALU can do an 8-bit addition subtraction logical or
shift operations in one cycle time There are five CPU regis-
ters
0
0 Hi-Z Input (TRI-STATE)
A is the 8-bit Accumulator register
0 1 Input with Weak Pull-Up
1 0 Push-Pull Zero Output
1 1 Push-Pull One Output
Three data memory address locations are allocated for this
port one each for data register 00D0 configuration regis-
ter 00D1 and the input pins 00D2
PC is the 15-bit Program Counter register
PU is the upper 7 bits of the program counter (PC)
PL is the lower 8 bits of the program counter (PC)
B is the 8-bit address register and can be auto incre-
mented or decremented
X is the 8-bit alternate address register and can be auto
incremented or decremented
PORT G is an 8-bit port with 6 I O pins (G0–G5) and 2 input
pins (G6 G7)
SP is the 8-bit stack pointer which points to the subroutine
stack (in RAM)
All eight G-pins have Schmitt Triggers on the inputs
There are two registers associated to configure the G port
a data register and a configuration register Therefore each
G port bit can be individually configured under software con-
trol as shown below
B X and SP registers are mapped into the on chip RAM
The B and X registers are used to address the on chip RAM
The SP register is used to address the stack in RAM during
subroutine calls and returns The SP must be preset by soft-
ware upon initialization
Port G
Config
0
0
Port G
Data
0
1
PORT G
MEMORY
Setup
The memory is separated into two memory spaces program
and data
Hi-Z Input (TRI-STATED)ataSheePtR4OUG.RcAoMmMEMORY
Input with Weak Pull-Up
Program memory consists of 768 x 8 ROM These bytes of
1
0 Push-Pull Zero Output
ROM may be instructions or constant data The memory is
addressed by the 15-bit program counter (PC) There are no
1 1 Push-Pull One Output ‘‘pages’’ of ROM the PC counts all 15 bits ROM can be
Three data memory address locations are allocated for this
indirectly read by the LAlD instruction for table lookup
port one for data register 00D4 one for configuration reg-
ister 00D5 and one for the input pins 00D6 Since G6
and G7 are Hi-Z input only pins any attempt by the user to
configure them as outputs by writing a one to the configura-
tion register will be disregarded Reading the G6 and G7
configuration bits will return zeroes Note that the chip will
be placed in the Halt mode by writing a ‘‘1’’ to the G7 data
bit
Six pins of Port G have alternate features
DATA MEMORY
The data memory address space includes on chip RAM I O
and registers Data memory is addressed directly by the in-
struction or indirectly through B X and SP registers The
device has 64 bytes of RAM Sixteen bytes of RAM are
mapped as ‘‘registers’’ these can be loaded immediately
decremented and tested Three specific registers X B and
SP are mapped into this space the other registers are avail-
able for general usage
G0 INTR (an external interrupt)
Any bit of data memory can be directly set reset or tested
G3 TIO (timer counter input output)
I O and registers (except A and PC) are memory mapped
G4 SO (MICROWIRE serial data output)
G5 SK (MICROWIRE clock I O)
therefore I O bits and register bits can be directly and indi-
vidually set reset and tested
G6 SI (MICROWIRE serial data input)
RESET
G7 CKO crystal oscillator output (selected by mask option)
or HALT restart input general purpose input (if clock op-
tion is R C- or external clock)
Pins G1 and G2 currently do not have any alternate func-
tions
The RESET input pin when pulled low initializes the micro-
controller Upon initialization the ports L and G are placed
in the TRl-STATE mode The PC PSW and CNTRL regis-
ters are cleared The data and configuration registers for
ports L and G are cleared The external RC network shown
in Figure 3 should be used to ensure that the RESET pin is
held low until the power supply to the chip stabilizes
5 http www national com
DataSheet4U.com
DataSheet4 U .com
DataShee
5 Page 
www.DataSheet4U.com
et4U.com
Interrupts (Continued)
Control Registers
DETECTION OF ILLEGAL CONDITIONS
CNTRL REGISTER (ADDRESS X’00EE)
Reading of undefined ROM gets zeroes The opcode for
software interrupt is zero If the program fetches instructions
from undefined ROM this will force a software interrupt
thus signalling that an illegal condition has occurred
Note A software interrupt is acted upon only when a timer or external inter-
rupt is not pending as hardware interrupts have priority over software
interrupt In addition the Global Interrupt bit is not set when a soft-
ware interrupt is being serviced thereby opening the door for the hard-
ware interrupts to occur The subroutine stack grows down for each
call and grows up for each return If the stack pointer is initialized to
2F Hex then if there are more returns than calls the stack pointer will
point to addresses 30 and 31 (which are undefined RAM) Undefined
RAM is read as all 1’s thus the program will return to address FFFF
This is a undefined ROM location and the instruction fetched will gen-
erate a software interrupt signalling an illegal condition The device
can detect the following illegal conditions
1 Executing from undefined ROM
2 Over ‘‘POP’’ing the stack by having more returns than calls
Illegal conditions may occur from coding errors ‘‘brown
out’’ voltage drops static supply noise etc When the soft-
ware interrupt occurs the user can re-initialize the stack
pointer and do a recovery procedure before restarting (this
recovery program is probably similar to RESET but might
not clear the RAM) Examination of the stack can help in
identifying the source of the error For example upon a soft-
ware interrupt if the SP e 30 31 it implies that the stack
was over ‘‘POP’’ed (with the SPe2F hex initially) If the SP
contains a legal value (less than or equal to the initialized
SP value) then the value in the PC gives a clue as to where
in the user program an attempt to access an illegal (an ad-
dress over 300 Hex) was made The opcode returned in this
case is 00 which is a software interrupt
The Timer and MICROWIRE control register contains the
following bits
SL1 and SL0 Select the MICROWIRE clock divide-by
(00 e 2 01 e 4 1x e 8)
IEDG
External interrupt edge polarity select
MSEL
Selects G5 and G4 as MICROWIRE signals
SK and SO respectively
TRUN
Used to start and stop the timer counter
(1 e run 0 e stop)
TC1 Timer Mode Control Bit
TC2 Timer Mode Control Bit
TC3 Timer Mode Control Bit
70
TC1 TC2 TC3 TRUN MSEL IEDG SL1 SL0
PSW REGISTER (ADDRESS X’00EF)
The PSW register contains the following select bits
GIE Global interrupt enable (enables interrupts)
ENI External interrupt enable
BUSY
MICROWIRE busy shifting flag
IPND
External interrupt pending
ENTI
Timer interrupt enable
TPND
Timer interrupt pending
(timer underflow or capture edge)
C Carry Flip flop
HC Half carry Flip flop
The detection of illegal conditions is illustrated with an ex-
ample
70
HC C TPND ENTI IPND BUSY ENI GIE
0043 CLRA
0044 RC
DataSheeTth4eUH.aclfo-Cmarry bit is also effected by all the instructions that
0045 JMP 04FF
effect the Carry flag The flag values depend upon the in-
0046 NOP
struction For example after executing the ADC instruction
the values of the Carry and the Half-Carry flag depend upon
When the device is executing this program it seemingly
the operands involved However instructions like SET C
‘‘locks-up’’ having executed a software interrupt To debug
this condition the user takes a look at the SP and the con-
and RESET C will set and clear both the carry flags Table V
lists out the instructions that effect the HC and the C flags
tents of the stack The SP has a legal value and the con-
tents of the stack are 04FF The perceptive user immediate-
TABLE V Instructions Effecting HC and C Flags
ly realizes that an illegal ROM location (04FF) was ac-
cessed and the opcode returned (00) was a software inter-
Instr
HC Flag
C Flag
rupt Another way to decode this is to run a trace and follow
the sequence of steps that ended in a software interrupt
ADC
Depends on Operands Depends on Operands
The damaging jump statement is changed
SUBC Depends on Operands Depends on Operands
SETC Set
Set
RESET C Set
Set
RRC
Depends on Operands Depends on Operands
MEMORY MAP
All RAM ports and registers (except A and PC) are mapped
into data memory address space
DataShee
DataSheet4U.com
DataSheet4 U .com
11 http www national com
11 Page | ||
| Páginas | Total 24 Páginas | |
| PDF Descargar | [ Datasheet COPC912CH.PDF ] | |
Hoja de datos destacado
| Número de pieza | Descripción | Fabricantes |
| COPC912C | 8-Bit Microcontroller | National Semiconductor |
| COPC912CH | 8-Bit Microcontroller | National Semiconductor |
| Número de pieza | Descripción | Fabricantes |
| SLA6805M | High Voltage 3 phase Motor Driver IC. |
 Sanken |
| SDC1742 | 12- and 14-Bit Hybrid Synchro / Resolver-to-Digital Converters. |
 Analog Devices |
|
DataSheet.es es una pagina web que funciona como un repositorio de manuales o hoja de datos de muchos de los productos más populares, |
| DataSheet.es | 2020 | Privacy Policy | Contacto | Buscar |