Datasheet.kr   

NT5DS16M8AT 데이터시트 PDF




Nanya Techology에서 제조한 전자 부품 NT5DS16M8AT은 전자 산업 및 응용 분야에서
광범위하게 사용되는 반도체 소자입니다.


PDF 형식의 NT5DS16M8AT 자료 제공

부품번호 NT5DS16M8AT 기능
기능 (NT5DS16M8AT / NT5DS32M4AT) 128Mb DDR SDRAM
제조업체 Nanya Techology
로고 Nanya Techology 로고


NT5DS16M8AT 데이터시트 를 다운로드하여 반도체의 전기적 특성과 매개변수에 대해 알아보세요.



전체 30 페이지수

미리보기를 사용할 수 없습니다

NT5DS16M8AT 데이터시트, 핀배열, 회로
www.DataSheet4U.com
NT5DS32M4AT
NT5DS16M8AT
128Mb Double Data Rate SDRAM
Features
CAS Latency and Frequency
CAS Latency
Maximum Operating Frequency (MHz)*
DDR266A
(-7K)
DDR266B
(-75B)
DDR200
(-8B)
2 133 100
2.5 143 133
* Values are nominal (exact tCK should be used).
100
125
• Double data rate architecture: two data transfers per
clock cycle
• Bidirectional data strobe (DQS) is transmitted and
received with data, to be used in capturing data at the
receiver
• DQS is edge-aligned with data for reads and is center-
aligned with data for writes
• Differential clock inputs (CK and CK)
• Four internal banks for concurrent operation
• Data mask (DM) for write data
• DLL aligns DQ and DQS transitions with CK transitions,
also aligns QFC transitions with CK during Read cycles
• Commands entered on each positive CK edge; data and
data mask referenced to both edges of DQS
• Burst lengths: 2, 4, or 8
• CAS Latency: 2, 2.5
• Auto Precharge option for each burst access
• Auto Refresh and Self Refresh Modes
• 15.6µs Maximum Average Periodic Refresh
Interval
• Supports tRAS lockout feature
• 2.5V (SSTL_2 compatible) I/O
• VDDQ = 2.5V ± 0.2V
• VDD = 2.5V ± 0.2V
• -7K parts support PC2100 modules.
-75B parts support PC2100 modules
-8B parts support PC1600 modules
Description
The 128Mb DDR SDRAM is a high-speed CMOS, dynamic
Read or Write command are used to select the bank and the
random-access memory containing 134,217,728 bits. It is
starting column location for the burst access.
internally configured as a quad-bank DRAM.
The DDR SDRAM provides for programmable Read or Write
The 128Mb DDR SDRAM uses a double-data-rate arcDhaitetacS- heet4bUur.sctolmengths of 2, 4 or 8 locations. An Auto Precharge func-
ture to achieve high-speed operation. The double data rate
tion may be enabled to provide a self-timed row precharge
DataShee
architecture is essentially a 2n prefetch architecture with an
that is initiated at the end of the burst access.
interface designed to transfer two data words per clock cycle
at the I/O pins. A single read or write access for the 128Mb
DDR SDRAM effectively consists of a single 2n-bit wide, one
clock cycle data transfer at the internal DRAM core and two
corresponding n-bit wide, one-half-clock-cycle data transfers
As with standard SDRAMs, the pipelined, multibank architec-
ture of DDR SDRAMs allows for concurrent operation,
thereby providing high effective bandwidth by hiding row pre-
charge and activation time.
at the I/O pins.
An auto refresh mode is provided along with a power-saving
A bidirectional data strobe (DQS) is transmitted externally,
along with data, for use in data capture at the receiver. DQS
is a strobe transmitted by the DDR SDRAM during Reads
power-down mode. All inputs are compatible with the JEDEC
Standard for SSTL_2. All outputs are SSTL_2, Class II com-
patible.
and by the memory controller during Writes. DQS is edge-
aligned with data for Reads and center-aligned with data for
Writes.
Note: The functionality described and the timing specifi-
cations included in this data sheet are for the DLL
Enabled mode of operation.
The 128Mb DDR SDRAM operates from a differential clock
(CK and CK; the crossing of CK going high and CK going
LOW is referred to as the positive edge of CK). Commands
(address and control signals) are registered at every positive
edge of CK. Input data is registered on both edges of DQS,
and output data is referenced to both edges of DQS, as well
as to both edges of CK.
Read and write accesses to the DDR SDRAM are burst ori-
ented; accesses start at a selected location and continue for
a programmed number of locations in a programmed
sequence. Accesses begin with the registration of an Active
command, which is then followed by a Read or Write com-
mand. The address bits registered coincident with the Active
command are used to select the bank and row to be
accessed. The address bits registered coincident with the
DataSheetR4UE.Vco1m.0
May, 2001
DataSheet4 U .com
1
© NANYA TECHNOLOGY CORP. All rights reserved.
NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice.




NT5DS16M8AT pdf, 반도체, 판매, 대치품
www.DataSheet4U.com
NT5DS32M4AT
NT5DS16M8AT
128Mb Double Data Rate SDRAM
Ordering Information
Part Number
NT5DS32M4AT-7K
NT5DS16M8AT-7K
CAS
Latency
Clock
(MHz)
143
CAS
Latency
Clock
(MHz)
133
Speed
DDR266A
Org.
x4
x8
Package
NT5DS32M4AT-75B
x4
2.5 133 2 100 DDR266B
66 pin TSOP-II
NT5DS16M8AT-75B
x8
NT5DS32M4AT-8B
NT5DS16M8AT-8B
125
x4
100 DDR200
x8
Note: At the present time, there are no plans to support DDR SDRAMs with the QFC function. All reference to QFC are for information.
et4U.com
DataSheet4U.com
DataShee
DataSheetR4UE.Vco1m.0
May, 2001
DataSheet4 U .com
4
© NANYA TECHNOLOGY CORP. All rights reserved.
NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice.

4페이지










NT5DS16M8AT 전자부품, 판매, 대치품
www.DataSheet4U.com
NT5DS32M4AT
NT5DS16M8AT
128Mb Double Data Rate SDRAM
Functional Description
The 128Mb DDR SDRAM is a high-speed CMOS, dynamic random-access memory containing 134, 217,728 bits. The 128Mb
DDR SDRAM is internally configured as a quad-bank DRAM.
The 128Mb DDR SDRAM uses a double-data-rate architecture to achieve high-speed operation. The double-data-rate architec-
ture is essentially a 2n prefetch architecture, with an interface designed to transfer two data words per clock cycle at the I/O
pins. A single read or write access for the 128Mb DDR SDRAM consists of a single 2n-bit wide, one clock cycle data transfer at
the internal DRAM core and two corresponding n-bit wide, one-half clock cycle data transfers at the I/O pins.
Read and write accesses to the DDR SDRAM are burst oriented; accesses start at a selected location and continue for a pro-
grammed number of locations in a programmed sequence. Accesses begin with the registration of an Active command, which is
then followed by a Read or Write command. The address bits registered coincident with the Active command are used to select
the bank and row to be accessed (BA0, BA1 select the bank; A0-A11 select the row). The address bits registered coincident
with the Read or Write command are used to select the starting column location for the burst access.
Prior to normal operation, the DDR SDRAM must be initialized. The following sections provide detailed infor-mation covering
device initialization, register definition, command descriptions and device operation.
Initialization
Only one of the following two conditions must be met.
• No power sequencing is specified during power up or power down given the following criteria:
VDD and VDDQ are driven from a single power converter output
VTT meets the specification
A minimum resistance of 42 ohms limits the input current from the VTT supply into any pin and
VREF tracks VDDQ /2
et4U.com
or
. The following relationships must be followed:
DataSheet4U.com
VDDQ is driven after or with VDD such that VDDQ < VDD + 0.3V
VTT is driven after or with VDDQ such that VTT < VDDQ + 0.3V
VREF is driven after or with VDDQ such that VREF < VDDQ + 0.3V
DataShee
The DQ and DQS outputs are in the High-Z state, where they remain until driven in normal operation (by a read access). After
all power supply and reference voltages are stable, and the clock is stable, the DDR SDRAM requires a 200µs delay prior to
applying an executable command.
Once the 200µs delay has been satisfied, a Deselect or NOP command should be applied, and CKE must be brought HIGH.
Following the NOP command, a Precharge ALL command must be applied. Next a Mode Register Set command must be
issued for the Extended Mode Register, to enable the DLL, then a Mode Register Set command must be issued for the Mode
Register, to reset the DLL, and to program the operating parameters. 200 clock cycles are required between the DLL reset and
any read command. A Precharge ALL command should be applied, placing the device in the “all banks idle” state
Once in the idle state, two auto refresh cycles must be performed. Additionally, a Mode Register Set command for the Mode
Register, with the reset DLL bit deactivated (i.e. to program operating parameters without resetting the DLL) must be performed.
Following these cycles, the DDR SDRAM is ready for normal operation.
DDR SDRAM’s may be reinitialized at any time during normal operation by asserting a valid MRS command to either the base
or extended mode registers without affecting the contents of the memory array. The contents of either the mode register or
extended mode register can be modified at any valid time during device operation without affecting the state of the internal
address refresh counters used for device refresh.
DataSheetR4UE.Vco1m.0
May, 2001
DataSheet4 U .com
7
© NANYA TECHNOLOGY CORP. All rights reserved.
NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice.

7페이지


구       성 총 30 페이지수
다운로드[ NT5DS16M8AT.PDF 데이터시트 ]

당사 플랫폼은 키워드, 제품 이름 또는 부품 번호를 사용하여 검색할 수 있는

포괄적인 데이터시트를 제공합니다.


구매 문의
일반 IC 문의 : 샘플 및 소량 구매
-----------------------------------------------------------------------

IGBT, TR 모듈, SCR 및 다이오드 모듈을 포함한
광범위한 전력 반도체를 판매합니다.

전력 반도체 전문업체

상호 : 아이지 인터내셔날

사이트 방문 :     [ 홈페이지 ]     [ 블로그 1 ]     [ 블로그 2 ]



관련 데이터시트

부품번호상세설명 및 기능제조사
NT5DS16M8AT

(NT5DSxxMxAx) 128Mb DDR333/300 SDRAM

Nanya Technology
Nanya Technology
NT5DS16M8AT

(NT5DS16M8AT / NT5DS32M4AT) 128Mb DDR SDRAM

Nanya Techology
Nanya Techology

DataSheet.kr       |      2020   |     연락처      |     링크모음      |      검색     |      사이트맵