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PDF NT5DS128M4CG Data sheet ( Hoja de datos )
| Número de pieza | NT5DS128M4CG | |
| Descripción | 512Mb DDR SDRAM | |
| Fabricantes | Nanya Techology | |
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NT5DS128M4CG
512Mb DDR SDRAM C-Die
Preliminary
Features
CAS Latency and Frequency
CAS
Latency
Maximum Operating
Frequency (MHz)
DDR400 (5T)
3 200
• DDR 512M bit, Die C, based on 90nm design rules
• Double data rate architecture: two data transfers per
clock cycle
• Bidirectional data strobe (DQS) is transmitted and
received with data, to be used in capturing data at the
receiver
• DQS is edge-aligned with data for reads and is center-
aligned with data for writes
• Differential clock inputs (CK and CK)
• Four internal banks for concurrent operation
• Data mask (DM) for write data
• DLL aligns DQ and DQS transitions with CK transitions
• Commands entered on each positive CK edge; data and
data mask referenced to both edges of DQS
• Burst lengths: 2, 4, or 8
• CAS Latency: 3
• Auto Precharge option for each burst access
• Auto Refresh and Self Refresh Modes
• 7.8µs Maximum Average Periodic Refresh Interval
• 2.5V (SSTL_2 compatible) I/O
• VDD = VDDQ = 2.6V ± 0.1V
• RoHS compliance
Description
Die C of 512Mb SDRAM devices based using DDR interface. The DDR SDRAM provides for programmable Read or Write
They are all based on Nanya’s 90 nm design process.
burst lengths of 2, 4, or 8 locations. An Auto Precharge func-
The 512Mb DDR SDRAM is a high-speed CMOS, dynamic
random-access memory containing 536,870,912 bits. It is
tion may be enabled to provide a self-timed row precharge
that is initiated at the end of the burst access.
internally configured as a quad-bank DRAM.
As with standard SDRAMs, the pipelined, multibank architec-
ture of DDR SDRAMs allows for concurrent operation,
The 512Mb DDR SDRAM uses a double-data-rate architec-
thereby providing high effective bandwidth by hiding row pre-
ture to achieve high-speed operation. The double dataDraattaeSheet4cUha.crgoemand activation time.
architecture is essentially a 2n prefetch architecture with an
DataShee
interface designed to transfer two data words per clock cycle An auto refresh mode is provided along with a power-saving
at the I/O pins. A single read or write access for the 512Mb
Power Down mode. All inputs are compatible with the JEDEC
DDR SDRAM effectively consists of a single 2n-bit wide, one Standard for SSTL_2. All outputs are SSTL_2, Class II com-
clock cycle data transfer at the internal DRAM core and two
patible.
corresponding n-bit wide, one-half-clock-cycle data transfers
at the I/O pins.
The functionality described and the timing specifications
included in this data sheet are for the DLL Enabled mode of
A bidirectional data strobe (DQS) is transmitted externally,
along with data, for use in data capture at the receiver. DQS
operation.
is a strobe transmitted by the DDR SDRAM during Reads
and by the memory controller during Writes. DQS is edge-
aligned with data for Reads and center-aligned with data for
Writes.
The 512Mb DDR SDRAM operates from a differential clock
(CK and CK; the crossing of CK going high and CK going
LOW is referred to as the positive edge of CK). Commands
(address and control signals) are registered at every positive
edge of CK. Input data is registered on both edges of DQS,
and output data is referenced to both edges of DQS, as well
as to both edges of CK.
Read and write accesses to the DDR SDRAM are burst ori-
ented; accesses start at a selected location and continue for
a programmed number of locations in a programmed
sequence. Accesses begin with the registration of an Active
command, which is then followed by a Read or Write com-
mand. The address bits registered coincident with the Active
command are used to select the bank and row to be
accessed. The address bits registered coincident with the
Read or Write command are used to select the bank and the
starting column location for the burst access.
DataSheetR4UE.Vco0m.1
January 23, 2006
1
© NANYA TECHNOLOGY CORP. All rights reserved.
NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice.
DataSheet4 U .com
1 page  
www.DataSheet4U.com
NT5DS128M4CG
512Mb DDR SDRAM C-Die
Preliminary
Block Diagram (128Mb x 4)
et4U.com
CKE
CK
CK
CS
WE
CAS
RAS
Mode
Registers
15 13
13
A0-A12,
BA0, BA1
15
2
2
12 Column-Address
Counter/Latch
Bank3
Bank1 Bank2
CK, CK
DLL
8192
Bank0
Memory
Array
Data
(8192 x 2048 x 8)
4
Sense Amplifiers
8
4
4
DQS
1
Generator
I/O Gating
DM Mask Logic
2048
(x8)
Column
Decoder
COL0 Input
DQS
8 Register
Write Mask 1
8
FIFO
&
Drivers
1
2
4
8
clk
out
clk
in
Data
4
1
1
1
4
4
4
11
CK, COL0
COL0
CK
1 DataSheet4U.com
1
DQ0-DQ3,
DM
DQS
Note: This Functional Block Diagram is intended to facilitate user understanding of the operation of
the device; it does not represent an actual circuit implementation.
Note: DM is a unidirectional signal (input only), but is internally loaded to match the load of the bidi-
rectional DQ and DQS signals.
DataShee
DataSheetR4UE.Vco0m.1
January 23, 2006
DataSheet4 U .com
5
© NANYA TECHNOLOGY CORP. All rights reserved.
NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice.
5 Page 
www.DataSheet4U.com
NT5DS128M4CG
512Mb DDR SDRAM C-Die
Preliminary
Extended Mode Register
The Extended Mode Register controls functions beyond those controlled by the Mode Register; these additional functions
include DLL enable/disable, bit A0; output drive strength selection, bit A1; and QFC output enable/disable, bit A2 (NTC
optional). These functions are controlled via the bit settings shown in the Extended Mode Register Definition. The Extended
Mode Register is programmed via the Mode Register Set command (with BA0 = 1 and BA1 = 0) and retains the stored informa-
tion until it is programmed again or the device loses power. The Extended Mode Register must be loaded when all banks are
idle, and the controller must wait the specified time before initiating any subsequent operation. Violating either of these require-
ments result in unspecified operation.
DLL Enable/Disable
The DLL must be enabled for normal operation. DLL enable is required during power up initialization, and upon returning to nor-
mal operation after having disabled the DLL for the purpose of debug or evaluation. The DLL is automatically disabled when
entering self refresh operation and is automatically re-enabled upon exit of self refresh operation. Any time the DLL is enabled,
200 clock cycles must occur to allow time for the internal clock to lock to the externally applied clock before a Read command
can be issued. This is the reason for introducing timing parameter tXSRD for DDR SDRAM’s (Exit Self Refresh to Read Com-
mand). Non- Read commands can be issued 2 clocks after the DLL is enabled via the EMRS command (tMRD) or 10 clocks after
the DLL is enabled via self refresh exit command (tXSNR, Exit Self Refresh to Non-Read Command).
Output Drive Strength
The normal drive strength for all outputs is specified to be SSTL_2, Class II.
QFC Enable/Disable (Not support in this product; Only for information)
et4U.com
The QFC signal is an optional DRAM output control uDseadtatoSihseoleatt4eUm.coodumle loads (DIMMs) from the system memory bus by
means of external FET switches when the given module (DIMM) is not being accessed. The QFC function is an optional feature
DataShee
for NANYA and is not included on all DDR SDRAM devices.
DataSheetR4UE.Vco0m.1
January 23, 2006
DataSheet4 U .com
11
© NANYA TECHNOLOGY CORP. All rights reserved.
NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice.
11 Page | ||
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