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PDF MC14553B Data sheet ( Hoja de datos )
| Número de pieza | MC14553B | |
| Descripción | 3-Digit BCD Counter | |
| Fabricantes | Motorola Semiconductors | |
| Logotipo |  |
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Hay una vista previa y un enlace de descarga de MC14553B (archivo pdf) en la parte inferior de esta página. Total 8 Páginas | ||
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MOTOROLA
SEMICONDUCTOR TECHNICAL DATA
MC14553B
3-Digit BCD Counter
The MC14553B 3–digit BCD counter consists of 3 negative edge triggered
BCD counters that are cascaded synchronously. A quad latch at the output
of each counter permits storage of any given count. The information is then
time division multiplexed, providing one BCD number or digit at a time. Digit
select outputs provide display control. All outputs are TTL compatible.
An on–chip oscillator provides the low–frequency scanning clock which
drives the multiplexer output selector.
This device is used in instrumentation counters, clock displays, digital
panel meters, and as a building block for general logic applications.
• TTL Compatible Outputs
• On–Chip Oscillator
• Cascadable
• Clock Disable Input
• Pulse Shaping Permits Very Slow Rise Times on Input Clock
• Output Latches
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎΕ Master Reset
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎMAXIMUM RATINGS* (Voltages Referenced to VSS)
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎSymbol
Parameter
Value
Unit
VDD DC Supply Voltage
– 0.5 to + 18.0
V
Vin, Vout Input or Output Voltage (DC or Transient)
Iin Input Current (DC or Transient), per Pin
– 0.5 to VDD + 0.5 V
DataS±h1e0 et4U.commA
Iout Output Current (DC or Transient), per Pin + 20 mA
PD Power Dissipation, per Package†
500 mW
Tstg Storage Temperature
– 65 to + 150
_C
TL Lead Temperature (8–Second Soldering)
260 _ C
* Maximum Ratings are those values beyond which damage to the device may occur.
†Temperature Derating:
Plastic “P and D/DW” Packages: – 7.0 mW/_ C From 65_ C To 125_ C
Ceramic “L” Packages: – 12 mW/_ C From 100_ C To 125_ C
TRUTH TABLE
Inputs
Master
Reset
Clock Disable
LE
0 00
0 00
0X1X
01
0
01
0
0 0XX
0 XX
0 XX 1
1 XX 0
X = Don’t Care
Outputs
No Change
Advance
No Change
Advance
No Change
No Change
Latched
Latched
Q0 = Q1 = Q2 = Q3 = 0
L SUFFIX
CERAMIC
CASE 620
P SUFFIX
PLASTIC
CASE 648
DW SUFFIX
SOIC
CASE 751G
ORDERING INFORMATION
MC14XXXBCP
MC14XXXBCL
MC14XXXBDW
Plastic
Ceramic
SOIC
TA = – 55° to 125°C for all packages.
BLOCK DIAGRAM
43
CIA CIB Q0
9
12 CLOCK
Q1 7
10 LE
Q2 6
Q3 5
11 DIS
O.F. 14
DS1 2
13 MR
DS2 1
DS3 15
VDD = PIN 16
VSS = PIN 8
DataShee
This device contains protection circuitry to
guard against damage due to high static
voltages or electric fields. However, pre-
cautions must be taken to avoid applications of
any voltage higher than maximum rated volt-
ages to this high–impedance circuit. For proper
v voperation, Vin and Vout should be constrained
to the range VSS (Vin or Vout) VDD.
Unused inputs must always be tied to an
appropriate logic voltage level (e.g., either VSS
or VDD). Unused outputs must be left open.
DataSheet4UR.cEoVm3
1/94
©MMOotoTrOolaR, IOncL. A199C5MOS LOGIC DATA
DataSheet4 U .com
MC14553B
1
1 page  
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OPERATING CHARACTERISTICS
The MC14553B three–digit counter, shown in Figure 3,
consists of three negative edge–triggered BCD counters
which are cascaded in a synchronous fashion. A quad latch
at the output of each of the three BCD counters permits stor-
age of any given count. The three sets of BCD outputs
(active high), after going through the latches, are time divi-
sion multiplexed, providing one BCD number or digit at a
time. Digit select outputs (active low) are provided for display
control. All outputs are TTL compatible.
An on–chip oscillator provides the low frequency scanning
clock which drives the multiplexer output selector. The fre-
quency of the oscillator can be controlled externally by a
capacitor between pins 3 and 4, or it can be overridden and
driven with an external clock at pin 4. Multiple devices can be
cascaded using the overflow output, which provides one
CLOCK
12
LATCH ENABLE
10
pulse for every 1000 counts.
The Master Reset input, when taken high, initializes the
three BCD counters and the multiplexer scanning circuit.
While Master Reset is high the digit scanner is set to digit
one; but all three digit select outputs are disabled to prolong
display life, and the scan oscillator is inhibited. The Disable
input, when high, prevents the input clock from reaching the
counters, while still retaining the last count. A pulse shaping
circuit at the clock input permits the counters to continue op-
erating on input pulses with very slow rise times. Information
present in the counters when the latch input goes high, will
be stored in the latches and will be retained while the latch
input is high, independent of other inputs. Information can be
recovered from the latches after the counters have been re-
set if Latch Enable remains high during the entire reset cycle.
C1A
ROSCSICLLAANTOR
4
3
C1B
R SCANNER
PULSE
C1 GENERATOR
et4U.com
PULSE
SHAPER
11
DISABLE
(ACTIVE
HIGH)
Q0
C Q1
Q2
R ÷ 10 Q3
UNITS
Q0
C Q1
Q2
R ÷ 10 Q3
TENS
QUAD
LATCH
DataSheet4U.com
MULTIPLEXER
QUAD
LATCH
9
Q0
7
Q1
BCD
OUTPUTS
(ACTIVE
HIGH)
6
Q2
DataShee
Q0
C Q1
Q2
R ÷ 10 Q3
HUNDREDS
QUAD
LATCH
5
Q3
DataSheet4U.com
13
MR
(ACTIVE HIGH)
14
OVERFLOW
2 1 15
DS1 DS2 DS3
(LSD) DIGIT SELECT (MSD)
(ACTIVE LOW)
Figure 3. Expanded Block Diagram
MOTOROLA CMOS LOGIC DATA
DataSheet4 U .com
MC14553B
5
5 Page | ||
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| PDF Descargar | [ Datasheet MC14553B.PDF ] | |
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