T7121 Datasheet PDF - Agere Systems
| Part Number | T7121 | |
| Description | T7121 HDLC Interface for ISDN | |
| Manufacturers | Agere Systems | |
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Data Sheet
April 1997
T7121 HDLC Interface for ISDN (HIFI-64)
Features
Description
s Low-cost device for B-channel (64 kbits/s) or
The T7121 HDLC Interface for ISDN (HIFI-64) con-
D-channel (16 kbits/s) data transport.
nects serial communications links carrying HDLC bit-
s Optional transparent mode—no HDLC framing is
performed.
synchronous data frames to 8-bit microcomputer sys-
tems. There is an optional transparent mode of oper-
ation in which no HDLC processing is performed on
s Frame sync (FS) allows a slot-select feature to
user data. The device communicates with the system
access an individual time slot in any TDM data
microprocessor as a memory-mapped peripheral and
stream (e.g., Lucent Technologies Microelectronics is controlled by reading and writing 19 internal regis-
Group Concentration Highway Interface [CHI] or
ters. The chip can be instructed to interrupt the
subset).
microprocessor when it detects certain events requir-
s Bit-masking option allows effective data rates of 8,
16, 24, 32, 40, 48, and 56 kbits/s.
ing microprocessor attention. The HDLC transmitter
and receiver are each buffered with 64-byte, first-in-
first-out (FIFO) memory storage. The 64-byte buffer DataShee
s Maximum data rate up to 4.096 MHz.
depth reduces the number of status polls or inter-
s SLuecrieanl tdIaStaD-NtralinnsefetrrapninsscefoivredrirTe7c2t5c0oCnn.DeacttaioSnhtoeetht4eU.coritmnhugeptomsvtiecorraoblpel rspoyrcsoetcesesmsosreeifndfitcebieyrfnatchcyee.,Tmthriacenromspmarojiotcraenbsdlsoocrerk,csiemaivrpeerov-
s Supports IOM2, K2, GCI, and SLD interface.
FIFO memory buffers, HDLC processor, and a con-
s Parallel microprocessor interface with either multi-
plexed or demultiplexed address and data lines for
easy interface with any microprocessor.
centration highway interface (see Figure 1). The
T7121 device is available in a 28-pin, plastic DIP or a
28-pin, plastic, small-outline, J-lead (SOJ) package
for surface mounting.
s Single interrupt output signal with seven maskable
interrupt conditions.
s Programmable interrupt modes.
s Memory-mapped read and write registers.
s TTL/CMOS compatible input/output.
s 3-state output pins to assist system diagnostics.
s Low-power 1.25 µm CMOS:
— 30 mW typical operation at 12 MHz.
— 5 mW standby mode (typical).
s HDLC transceiver:
— Stand-alone HDLC framing operation.
— 64-byte FIFO in both transmit and receive direc-
tions.
— Supports block-move instruction.
— Multiple frames allowed in FIFO.
— Programmable FIFO full- and empty-level inter-
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Data Sheet
April 1997
T7121 HDLC Interface for ISDN (HIFI-64)
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Pin Information (continued)
Table 2. Pin Descriptions
Pin
1
2—5,
7—10
6, 22
11
12
13
14
15
16
Symbol
ALE
AD0—AD7
VSS
WR
RD
CS
INT
RESET
FS
Type
Name/Function
I Address Latch Enable. A high-to-low transition on this pin latches the register
address on pins AD3—AD0. ALE should be held high in the demultiplexed (sep-
arate address/data) mode. ALE latches the address regardless of the state of
CS.
I/O Address/Data Bus. The data bus direction is controlled by the logic states of
the CS, RD, and WR pins. Microprocessors using a multiplexed bus supply
address information during read or write cycles on AD6, AD3—AD0 synchro-
nized to the ALE signal. During read cycles, data is available to the micropro-
cessor on AD7—AD0. During write cycles, data is supplied by the
microprocessor on these lines. When CS is not active, the AD7—AD0 pins are
placed in a high-impedance state (3-state). AD0 is the least significant
address/data bit.
Block move is available in MUXed address and data mode by setting the BM bit
in register 0 (R0—B3) to 1 and holding AD6 high during the address cycle of the
ALE. All writes then go directly to the transmit FIFO, and all reads address the
receive FIFO. Normal ALE mode addressing is accomplished by holding AD6
low during the ALE address cycle. Block move can be disabled by clearing the
BM bit to 0.
— Ground.
DataShee
I Write (Active-Low). This signal controls when data is written to the registers.
When CSDaantadSWhReeatr4eUlo.cwo,mvalid data is supplied on lines AD7—AD0 by the
microprocessor. The chip latches the data on the rising edge of WR.
I Read (Active-Low). This signal is used to read data from the registers. When
CS and WR are low, the chip makes the requested data available on lines AD7—
AD0 to be read by the microprocessor.
I Chip Select (Active-Low). This signal must be low for the internal registers to
be read or written.
O Interrupt. An interrupt signal is generated when any of the interrupting condi-
tions are true. The interrupt signal remains active until the microprocessor reads
the interrupt status register (R15) if DINT (R0—B0) = 0, or until the condition
causing the interrupt is alleviated if DINT = 1. Interrupts can be masked by
appropriately setting the corresponding interrupt enable bits in the interrupt
mask register (R14). The polarity of the interrupt signal output is controlled by
the IPOL bit in register 0 (R0—B1). This pin is not an open-drain output.
I Reset. A high on this pin resets the device and forces a high-impedance
(3-state) condition on all outputs. All register bits are forced to their reset values.
(See Register section for more details.) A reset must be performed upon pow-
erup. A full chip reset occurs with or without a clock input.
I Frame Synchronization. This signal marks the beginning of a TDM highway
frame. The polarity of the input pulse can be adjusted via the FSPOL bit in regis-
ter 0 (R0—B6). Individual time slots are assigned relative to the detection of FS
by the use of registers 7—11. When HWYEN (R0—B7) is 0, the input to this pin
is ignored.
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