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부품번호 AN1568 기능
기능 Interfacing Between LVDS and ECL
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AN1568 데이터시트, 핀배열, 회로
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AN1568/D
Interfacing Between LVDS
and ECL
Prepared by: Paul Lee
Logic Applications Engineer
ON Semiconductor
http://onsemi.com
APPLICATION NOTE
Introduction
ECL levels
Recent growth in high−speed data transmission between
Today’s applications typically use ECL devices in the
high−speed ICs demand more bandwidth than ever before PECL mode. PECL (Positive ECL) is nothing more than
while still maintaining high performance, low power supplying any ECL device with a positive power supply
consumption and good noise immunity. Emitter Coupled
Logic (ECL) recognized the challenge and provided high
(VCC = +5.0 V, VEE = 0 V). In addition, ECL uses differential
data transmission technology, which results in better noise
performance and good noise immune devices. ECL immunity. Since the common mode noise is coupled onto the
migrated toward low voltages to reduce the power differential interconnect, it will be seen as a common mode
consumption and to keep up with current technology trends modulation and will be rejected.
by offering 3.3 V and 2.5 V Low Voltage ECL (LVECL)
With the trend towards low voltage systems, a new
devices.
generation of ECL circuitry has been developed. The Low
LVDS (Low Voltage Differential Signaling) technology Voltage NECL (LVNECL) devices work using negative
also addresses the needs of current high perforDmaatnacSeheet4U3..c3oVmor –2.5 V power supply, or more popular positive
applications. LVDS as specified in ANSI/TIA/EIA−644 by power supplies, VCC = +3.3 V or +2.5 V and VEE = GND as
Data Transmission Interface committee TR30.2 and IEEE LVPECL. LVECL maintains 750 mV output swing with a
1596.3 SCI−LVDS by IEEE Scalable Coherent Interface
standard (SCI) is a high speed, low power interface that is a
0.9 V offset from VCC, which makes them ideal as peripheral
components.
solution in many application areas. LVDS provides an
The temperature compensated (100EL, 100LVEL,
output swing of 250 mV to 400 mV with a DC offset of 1.2 V. 100EP, 100LVEP) output DC levels for the different supply
External resistor components are required for levels are shown in Table 1. ECL outputs are designed as an
board−to−board data transfer or clock distribution.
open emitter, requiring a DC path to a more negative supply
LVECL and LVDS are both differential voltage signals,
but with different output amplitude and offset. The purpose
than VOL. (see AND8020 for ECL Termination
information).
of this documentation is to show the interfacing between
LVECL and LVDS. In addition, it gives interface
ECL standard DC input levels are also relative to VCC.
Many devices are available with Voltage Input HIGH
recommendations to and from 5.0 V supplied PECL devices
and negative supplied ECL or NECL
Common Mode Range (VIHCMR). These differential inputs
allow processing signals with small VINPPMIN (down to
200 mV, 150 mV or even 50 mV signal levels) within an
appropriate offset range. The VIHCMR ranges of ECL
devices are listed in each respective data sheets.
DataShee
DataSheet4U.com
© Semiconductor Components Industries, LLC, 2003
October, 2003 − Rev. 8
DataSheet4 U .com
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Publication Order Number:
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AN1568/D
Capacitive Coupling LVDS to ECL
Capacitive Coupling LVDS to ECL Using V BB
Several ECL devices provide an externally accessible
VBB (VBB VCC –1.3V) reference voltage. This ECL
reference voltage can be used for differential capacitive
coupling. The 10 nF capacitor can be used to decouple VBB
to GND. (Figure 3)
Z = 50 W
10 pF
LVDS
Z = 50 W
100 W
10 pF
1 kW
ECL
1 kW
VBB
In the layout for both interfaces, the resistors and the
capacitors should be located as close as possible to the ECL
input to insure reduced reflection and increased signal
integrity.
Capacitive Coupling ECL to LVDS
The ECL output requires a DC current path to VEE;
therefore, the pulldown termination resistors, RT, are
connected to VEE. The Thevenin resistor pair represent the
termination of the transmission line Z = R1 || R2 and
generates an appropriate DC offset level of 1.2 V. (Figure 5)
3.3 V
R1
130 W
Z = 50 W 10 pF
R1
130 W
et4U.com
10 nF
Figure 3. Capacitive Coupling LVDS to ECL
Using VBB
ECL
RT
Z = 50 W
10 pF
RT R2
80 W
LVDS
R2
80 W
Capacitive Coupling LVDS to ECL with External
VEE
Biasing
Figure 5. Capacitive Coupling ECL to LVDS
If VBB reference voltage is not available, equivalent DC
voltage can be generated using a resistor divider network.
An example of capacitive coupled LVPECL
The resistor values depend on VCC and VEE voltages
(ECLinPS PlusDevice) to LVDS is shown below.
(Table 3). Stability is enhanced during null signal conDdaittioanSsheet4(UF.icgoumre 6)
if a 50 mV differential voltage is maintained between the
divider networks. (Figure 4)
Table 3. Examples:
2.5 V or 3.3 V
3.3 V
3.3 V
VCC = GND
VCC = GND
VCC = GND
VEE = −5.0 V
VEE = −3.3 V
VEE = −2.5 V
R1 = 1.2 kW
R1 = 680 W
R1 = 100 W
R2 = 3.4 kW
R2 = 1.0 kW
R2 = 90 W
R2
43 W
R3
3.9 kW
R3
3.9 kW
VCC
LVPECL
10 pF
R2
LVDS
43 W
Z = 50 W
R1
10 pF
R1
R1
237 W
10 pF
R1 R4
237 W 2 kW
R4
2 kW
DataShee
LVDS
Z = 50 W
100 W
10 pF
R2
ECL
R2
VEE
Figure 4. Capacitive Coupling LVDS to ECL with
External Biasing
Figure 6. Capacitive Coupling LVPECL to LVDS
Capacitive Coupling ECL to LVDS Using VOS
Reference Voltage
Some LVDS devices supply external offset reference
voltage (VOS), which can be used for capacitive coupling.
When the transmission line is very short, a parallel
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3.3 V LVPECL
2.37 V
850 mV
LVDS
VCM(LVPECL)
1.52 V
VCM(LVDS)
1.39 V
320 mV
1.07 V
Figure 16. PSPICE Simulated Voltage Levels of
3.3 V LVPECL to LVDS Interface with Example
Resistor Values
Interfacing from LVDS to LVPECL
The input common mode range of the low voltage ECL
line receivers are wide enough to process LVDS signals.
(Figure 17)
3.3 V
Z = 50 W
2.5 V or 3.3 V
LVDS
Z = 50 W
100 W LVPECL
Interfacing from PECL to LVDS
Since the output levels VOH and VOL of 5 V PECL are
more positive than the input range of LVDS receiver, special
interface is required. (See Figure 18). Furthermore, the open
emitter design of the ECL output structure need proper
termination, which can be incorporated with the resistor
divider network to generate a proper LVDS DC levels (eq.
3).
R1 ) R2 + RT
(eq. 3)
The resistor divider network will divide the output
common mode voltage of PECL (VCM(PECL)) to input
common mode voltage of LVDS (VCM(LVDS)).
R2
R1 ) R2
+
VCM(LVDS)
VCM(PECL)
Where:
RT = Termination Resistor
VCM(PECL) = Common Mode Voltage
VCM(LVDS) = Common Mode Voltage
(eq. 4)
The above equations may give non—standard resistor
values and when choosing resistors off the shelf, to avoid
cutoff condition under worst−case scenario.
5V
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Figure 17. Interfacing LVDS to LVPECL
PECL
This direct interface is possible for all ECL devices with
sufficiently low minimum differential input HIGH common
mode range inputs. A differentially operated receiver’s
VIHCMR minimum must be 1.2 V or less (see device data
sheet).
ZO
ZO
R1
VCC
ZO
R1
ZO
LVDS
Table 4. LVDS Input Compatible Devices
EP14
LVEP210S LVEL37 EL56
R2 R2
EP809
LVE222
LVEL39 EL91
LVEP11
LVEP14
LVEP16
LVEP17
LVEL05
LVEL11
LVEL13
LVEL14
LVEL40
LVEL51
LVEL56
LVEL92
SG11
SG14
SG16
SG16M
Figure 18. Interfacing 5 V PECL to LVDS
Examples:
For 50 W controlled impedance, the resistor values for 5V
PECL converted to LVDS voltage levels are as follows:
LVEP34
LVEP56
LVEP91
LVEP111
LVEP210
LVEL16
LVEL17
LVEL29
LVEL32
LVEL33
EL13
EL14
EL17
EL29
EL39
SG16VS
SG53A
SG72A
SG86A
SG111
R1 = 134 W
R2 = 66 W
RT = 200 W
VCM(PECL) = 3.65 V
VCM(LVDS) = 1.2 V
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부품번호상세설명 및 기능제조사
AN1568

Interfacing Between LVDS and ECL

ON Semiconductor
ON Semiconductor
AN1568D

Interfacing Between LVDS and ECL

ON Semiconductor
ON Semiconductor

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