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PDF DAC8554 Data sheet ( Hoja de datos )
| Número de pieza | DAC8554 | |
| Descripción | VOLTAGE OUTPUT DIGITAL-TO-ANALOG CONVERTER | |
| Fabricantes | Burr-Brown Corporation | |
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Hay una vista previa y un enlace de descarga de DAC8554 (archivo pdf) en la parte inferior de esta página. Total 26 Páginas | ||
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BurrĆBrown Products
from Texas Instruments
DAC8554
SLAS431A – JUNE 2005 – REVISED AUGUST 2005
16-BIT, QUAD CHANNEL, ULTRALOW GLITCH, VOLTAGE OUTPUT
DIGITAL-TO-ANALOG CONVERTER
FEATURES
DESCRIPTION
• Relative Accuracy: 12 LSB (Max)
The DAC8554 is a 16-bit, quad channel, voltage
• Glitch Energy: 0.15 nV-s
• Power Supply: +2.7 V to +5.5 V
• MicroPower Operation: 850 µA at 5 V
output, digital-to-analog converter (DAC), offering
low-power operation and a flexible serial host
interface. It offers monotonicity, good linearity, and
exceptionally low glitch. Each on-chip precision out-
• 16-Bit Monotonic Over Temperature
put amplifier allows rail-to-rail output swing to be
• Settling Time: 10 µs to ±0.003% FSR
• Ultra-Low AC Crosstalk: –100 dB Typ
• Power-On Reset to Zero-Scale
achieved over the supply range of 2.7 V to 5.5 V. The
device supports a standard 3-wire serial interface
capable of operating with input data clock frequencies
up to 50 MHz for IOVDD = 5 V.
• On-Chip Output Buffer Amplifier With
Rail-to-Rail Operation
The DAC8554 requires an external reference voltage
to set the output range of each DAC channel. Also
• Double Buffered Input Architecture
• Simultaneous or Sequential Output Update
and Power-Down
• 16-Channel Broadcast Capability
incorporated into the device is a power-on reset
circuit which ensures that the DAC outputs power up
at zero-scale and remain there until a valid write
takes place. The DAC8554 provides a per channel
power-down feature, accessed over the serial
• Schmitt-Triggered Inputs
• SPI Compatible Serial Interface: Up to 50 MHz
interface, that reduces the current consumption to
200 nA per channel at 5 V.
• 1.8 V to 5.5 V Logic Compatibility
• Available in a TSSOP-16 Package
The low-power consumption of this device in normal
DataSheet4oUp.ceoramtion makes it ideally suited to portable battery-
operated equipment and other low-power appli-
APPLICATIONS
• Portable Instrumentation
• Closed-Loop Servo-Control
• Process Control
cations. The power consumption is 4.25 mW at 5 V,
reducing to 4 µW in power-down mode.
The DAC8554 is available in a TSSOP-16 package
with a specified operating temperature range of
–40°C to 105°C.
• Data Acquisition Systems
• Programmable Attenuation
• PC Peripherals
AVDD IOVDD
VrefH
DataShee
Data
Buffer A
DAC
Register A
DAC A
Data
Buffer D
DAC
Register D
DAC D
18
VOUTA
VOUTB
VOUTC
VOUTD
SYNC
SCLK
DIN
24-Bit
Serial-to-
Parallel Shift
Register
8
Buffer
Control
Register
Control
Power-Down
Control Logic
Resistor
Network
A0 A1 LDAC ENABLE VrefL
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
SPI, QSPI are trademarks of Motorola.
DataSheet4UM.iccroomwire is a trademark of National Semiconductor.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2005, Texas Instruments Incorporated
1 page  
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PIN NAME
16 LDAC
DAC8554
SLAS431A – JUNE 2005 – REVISED AUGUST 2005
PIN DESCRIPTIONS (continued)
DESCRIPTION
Load DACs, rising edge triggered, loads all DAC registers.
et4U.com
TIMING REQUIREMENTS(1)(2)
AVDD = 2.7 V to 5.5 V, all specifications –40°C to 105°C (unless otherwise noted)
PARAMETER
TEST CONDITIONS
t
(3)
1
t2
t3
t4
t5
t6
t7
t8
t9
SCLK cycle time
IOVDD = AVDD = 2.7 V to 3.6 V
IOVDD = AVDD = 3.6 V to 5.5 V
SCLK HIGH time
IOVDD = AVDD = 2.7 V to 3.6 V
IOVDD = AVDD = 3.6 V to 5.5 V
SCLK LOW time
IOVDD = AVDD = 2.7 V to 3.6 V
IOVDD = AVDD = 3.6 V to 5.5 V
SYNC falling edge to SCLK rising edge setup time
IOVDD = AVDD = 2.7 V to 3.6 V
IOVDD = AVDD = 3.6 V to 5.5 V
Data setup time
IOVDD = AVDD = 2.7 V to 3.6 V
IOVDD = AVDD = 3.6 V to 5.5 V
Data hold time
IOVDD = AVDD = 2.7 V to 3.6 V
IOVDD = AVDD = 3.6 V to 5.5 V
24th SCLK falling edge to SYNC rising edge
IOVDD = AVDD = 2.7 V to 3.6 V
IOVDD = AVDD = 3.6 V to 5.5 V
Minimum SYNC HIGH time
24th SCLK falling edge to SYNC falling edge
IOVDD = AVDD = 2.7 V to 3.6 V
DataSIOheVeDDt4=UA.VcDoDm= 3.6 V to 5.5 V
IOVDD = AVDD = 2.7 V to 5.5 V
MIN TYP MAX UNIT
40
ns
20
20
ns
10
20
ns
10
0
ns
0
5
ns
5
4.5
ns
4.5
0
ns
0
40
ns
20
130 ns
(1) All input signals are specified with tR = tF = 3 ns (10% to 90% of AVDD) and timed from a voltage level of (VIL + VIH)/2.
(2) See Serial Write Operation timing diagram.
(3) Maximum SCLK frequency is 50 MHz at IOVDD = AVDD = 3.6 V to 5.5 V and 25 MHz at IOVDD = AVDD = 2.7 V to 3.6 V.
SERIAL WRITE OPERATION
SCLK
SYNC
DIN
1
t8
t4
DB23
t6
t5
t3
t1
t2
24
t7
DB0
t9
DB23
DataShee
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5
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TYPICAL CHARACTERISTICS (continued)
At TA = 25°C, unless otherwise noted
HALF-SCALE SETTLING TIME: 2.7 V RISING EDGE
Trigger Pulse
2.7 V/div
Rising
Edge
0.5 V/div
VDD = 2.7 V
VREF = 2.5 V
From code; 4000
To code: CFFF
Zoomed Rising Edge
1 mV / div
Time − 2 ms/div
Figure 31.
GLITCH ENERGY: 5 V, 1 LSB STEP, RISING EDGE
DAC8554
SLAS431A – JUNE 2005 – REVISED AUGUST 2005
HALF-SCALE SETTLING TIME: 2.7 V FALLING EDGE
Falling
Edge
0.5 V/div
Trigger Pulse
2.7 V/div
AVDD = 2.7 V,
Vref = 2.5 V,
From Code: CFFF
To Code: 4000
Zoomed Falling Edge
1 mV/div
Time (2 µs/div)
Figure 32.
GLITCH ENERGY: 5 V, 1 LSB STEP, FALLING EDGE
et4U.com
DataSheet4U.com
AVDD = 5 V,
Vref = 4.096 V
From Code: 7FFF
To Code: 8000
Glitch: 0.08 nV-s
AVDD = 5 V,
Vref = 4.096 V
From Code: 8000
To Code: 7FFF
Glitch: 0.16 nV-s
Measured Worst Case
DataShee
Time 400 ns/div
Figure 33.
GLITCH ENERGY: 5 V, 16 LSB STEP, RISING EDGE
Time 400 ns/div
Figure 34.
GLITCH ENERGY: 5 V, 16 LSB STEP, FALLING EDGE
AVDD = 5 V,
Vref = 4.096 V
From Code: 8000
To Code: 8010
Glitch: 0.04 nV-s
AVDD = 5 V,
Vref = 4.096 V
From Code: 8010
To Code: 8000
Glitch: 0.08 nV-s
Time 400 ns/div
Figure 35.
Time 400 ns/div
Figure 36.
DataSheet4U.com
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| Páginas | Total 26 Páginas | |
| PDF Descargar | [ Datasheet DAC8554.PDF ] | |
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