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PDF LTC2292 Data sheet ( Hoja de datos )
| Número de pieza | LTC2292 | |
| Descripción | (LTC2291 - LTC2293) 65/40/25Msps Low Power 3V ADCs | |
| Fabricantes | Linear Technology | |
| Logotipo |  |
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Hay una vista previa y un enlace de descarga de LTC2292 (archivo pdf) en la parte inferior de esta página. Total 28 Páginas | ||
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LTC2293/LTC2292/LTC2291
Dual 12-Bit, 65/40/25Msps
Low Power 3V ADCs
FEATURES
DESCRIPTIO
■ Integrated Dual 12-Bit ADCs
The LTC®2293/LTC2292/LTC2291 are 12-bit 65Msps/
■ Sample Rate: 65Msps/40Msps/25Msps
40Msps/25Msps, low power dual 3V A/D converters de-
■ Single 3V Supply (2.7V to 3.4V)
signed for digitizing high frequency, wide dynamic range
■ Low Power: 400mW/235mW/150mW
signals. The LTC2293/LTC2292/LTC2291 are perfect for
■ 71dB SNR up to 70MHz Input
demanding imaging and communications applications
■ 85dB SFDR up to 70MHz Input
with AC performance that includes 71dB SNR and 85dB
■ 110dB Channel Isolation at 100MHz
SFDR for signals well beyond the Nyquist frequency.
■ Multiplexed or Separate Data Bus
■ Flexible Input: 1VP-P to 2VP-P Range
■ 575MHz Full Power Bandwidth S/H
■ Clock Duty Cycle Stabilizer
DC specs include ±0.3LSB INL (typ), ±0.15LSB DNL (typ)
and no missing codes over temperature. The transition
noise is a low 0.25LSBRMS.
■ Shutdown and Nap Modes
A single 3V supply allows low power operation. A separate
■ Pin Compatible Family
output supply allows the outputs to drive 0.5V to 3.3V
80Msps: LTC2294 (12-Bit), LTC2299 (14-Bit)
logic. An optional multiplexer allows both channels to
65Msps: LTC2293 (12-Bit), LTC2298 (14-Bit)
share a digital output bus.
40Msps: LTC2292 (12-Bit), LTC2297 (14-Bit)
A single-ended CLK input controls converter operation. An DataShee
25Msps: LTC2291 (12-Bit), LTC2296 (14-Bit)
optional clock duty cycle stabilizer allows high perfor-
10Msps: LTC2290 (12-Bit), LTC2295 (14-Bit) DataSheet4mUa.cnocme at full speed for a wide range of clock duty cycles.
■ 64-Pin (9mm × 9Umm) QFN Package
, LTC and LT are registered trademarks of Linear Technology Corporation.
APPLICATIO S
All other trademarks are the property of their respective owners.
■ Wireless and Wired Broadband Communication
■ Imaging Systems
■ Spectral Analysis
■ Portable Instrumentation
TYPICAL APPLICATIO
ANALOG
INPUT A
+
INPUT
S/H
–
CLK A
CLK B
CLOCK/DUTY CYCLE
CONTROL
CLOCK/DUTY CYCLE
CONTROL
ANALOG
INPUT B
DataSheet4U.com
+
INPUT
S/H
–
12-BIT
PIPELINED
ADC CORE
12-BIT
PIPELINED
ADC CORE
OUTPUT
DRIVERS
OVDD
D11A
•••
D0A
OGND
MUX
OUTPUT
DRIVERS
OVDD
D11B
•••
D0B
OGND
229321 TA01
LTC2293: SNR vs Input Frequency,
–1dB, 2V Range, 65Msps
72
71
70
69
68
0
50 100 150
INPUT FREQUENCY (MHz)
200
229321 TA02
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LTC2293/LTC2292/LTC2291
POWER REQUIRE E TS The ● denotes the specifications which apply over the full operating temperature
range, otherwise specifications are at TA = 25°C. (Note 8)
SYMBOL PARAMETER
CONDITIONS
LTC2293
LTC2292
LTC2291
MIN TYP MAX MIN TYP MAX MIN TYP MAX
UNITS
VDD
Analog Supply
(Note 9)
Voltage
● 2.7 3 3.4 2.7 3 3.4 2.7 3 3.4
V
OVDD
Output Supply
Voltage
(Note 9)
● 0.5 3 3.6 0.5 3 3.6 0.5 3 3.6
V
IVDD
PDISS
PSHDN
Supply Current
Power Dissipation
Shutdown Power
(Each Channel)
Both ADCs at fS(MAX)
Both ADCs at fS(MAX)
SHDN = H,
OE = H, No CLK
●
●
133 150
400 450
2
78 95
235 285
2
50 60
150 180
2
mA
mW
mW
PNAP Nap Mode Power SHDN = H,
(Each Channel) OE = L, No CLK
15 15 15 mW
WU
TI I G CHARACTERISTICS The ● denotes the specifications which apply over the full operating temperature
range, otherwise specifications are at TA = 25°C. (Note 4)
SYMBOL
fs
et4U.com tL
tH
tAP
tD
tMD
Pipeline
Latency
PARAMETER
CONDITIONS
LTC2293
MIN TYP MAX
Sampling Frequency (Note 9)
●1
65
CLK Low Time
CLK High Time
Duty Cycle Stabilizer Off
Duty Cycle Stabilizer On
(Note 7)
Duty Cycle Stabilizer Off
Duty Cycle Stabilizer On
(Note 7)
● 7.3 7.7 500
● 5 7.7 500
DataSheet4U.com
● 7.3 7.7 500
● 5 7.7 500
Sample-and-Hold
Aperture Delay
0
CLK to DATA Delay
MUX to DATA Delay
Data Access Time
After OE↓
CL = 5pF (Note 7)
CL = 5pF (Note 7)
CL = 5pF (Note 7)
● 1.4 2.7 5.4
● 1.4 2.7 5.4
● 4.3 10
BUS Relinquish Time (Note 7)
● 3.3 8.5
6
LTC2292
MIN TYP MAX
1 40
11.8 12.5 500
5 12.5 500
11.8 12.5 500
5 12.5 500
0
1.4 2.7 5.4
1.4 2.7 5.4
4.3 10
3.3 8.5
6
LTC2291
MIN TYP MAX
1 25
18.9 20 500
5 20 500
18.9 20 500
5 20 500
0
1.4 2.7 5.4
1.4 2.7 5.4
4.3 10
3.3 8.5
6
UNITS
MHz
ns DataShee
ns
ns
ns
ns
ns
ns
ns
ns
Cycles
Note 1: Absolute Maximum Ratings are those values beyond which the life
of a device may be impaired.
Note 2: All voltage values are with respect to ground with GND and OGND
wired together (unless otherwise noted).
Note 3: When these pin voltages are taken below GND or above VDD, they
will be clamped by internal diodes. This product can handle input currents
of greater than 100mA below GND or above VDD without latchup.
Note 4: VDD = 3V, fSAMPLE = 65MHz (LTC2293), 40MHz (LTC2292), or
25MHz (LTC2291), input range = 2VP-P with differential drive, unless
otherwise noted.
Note 5: Integral nonlinearity is defined as the deviation of a code from a
straight line passing through the actual endpoints of the transfer curve.
The deviation is measured from the center of the quantization band.
Note 6: Offset error is the offset voltage measured from –0.5 LSB when
the output code flickers between 0000 0000 0000 and 1111 1111 1111.
Note 7: Guaranteed by design, not subject to test.
Note 8: VDD = 3V, fSAMPLE = 65MHz (LTC2293), 40MHz (LTC2292), or
25MHz (LTC2291), input range = 1VP-P with differential drive. The supply
current and power dissipation are the sum total for both channels with
both channels active.
Note 9: Recommended operating conditions.
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LTC2293/LTC2292/LTC2291
TYPICAL PERFOR A CE CHARACTERISTICS
LTC2291: SFDR vs Input Level,
fIN = 5MHz, 2V Range, 25Msps
120
110 dBFS
100
90
80 dBc
70
60
90dBc SFDR
50 REFERENCE LINE
40
30
20
–60
–50 – 40 –30 –20
INPUT LEVEL (dBFS)
–10
0
229321 G45
LTC2291: IVDD vs Sample Rate,
5MHz Sine Wave Input, –1dB
70
60
2V RANGE
50
1V RANGE
40
30
0 5 10 15 20 25 30 35
SAMPLE RATE (Msps)
229321 G46
LTC2291: IOVDD vs Sample Rate,
5MHz Sine Wave Input, –1dB,
OVDD = 1.8V
6
4
2
0
0 5 10 15 20 25 30 35
SAMPLE RATE (Msps)
229321 G47
PI FU CTIO S
et4U.com AINA+ (Pin 1): Channel A Positive Differential Analog chip capacitor as close to the pin as possible. Also bypass DataShee
Input.
DataSheet4toU.Pcionms 13, 14 with an additional 2.2µF ceramic chip ca-
AINA– (Pin 2): Channel A Negative Differential Analog pacitor and to ground with a 1µF ceramic chip capacitor.
Input.
REFHB (Pins 13, 14): Channel B High Reference. Short
REFHA (Pins 3, 4): Channel A High Reference. Short
together and bypass to Pins 5, 6 with a 0.1µF ceramic chip
capacitor as close to the pin as possible. Also bypass to
Pins 5, 6 with an additional 2.2µF ceramic chip capacitor
and to ground with a 1µF ceramic chip capacitor.
REFLA (Pins 5, 6): Channel A Low Reference. Short
together and bypass to Pins 11, 12 with a 0.1µF ceramic
chip capacitor as close to the pin as possible. Also bypass
to Pins 11, 12 with an additional 2.2µF ceramic chip ca-
pacitor and to ground with a 1µF ceramic chip capacitor.
AINB– (Pin 15): Channel B Negative Differential Analog
Input.
together and bypass to Pins 3, 4 with a 0.1µF ceramic chip AINB+ (Pin 16): Channel B Positive Differential Analog
capacitor as close to the pin as possible. Also bypass to Input.
Pins 3, 4 with an additional 2.2µF ceramic chip capacitor
and to ground with a 1µF ceramic chip capacitor.
VDD (Pins 7, 10, 18, 63): Analog 3V Supply. Bypass to
GND with 0.1µF ceramic chip capacitors.
CLKA (Pin 8): Channel A Clock Input. The input sample
GND (Pins 17, 64): ADC Power Ground.
SENSEB (Pin 19): Channel B Reference Programming Pin.
Connecting SENSEB to VCMB selects the internal reference
and a ±0.5V input range. VDD selects the internal reference
and a ±1V input range. An external reference greater than
starts on the positive edge.
0.5V and less than 1V applied to SENSEB selects an input
CLKB (Pin 9): Channel B Clock Input. The input sample range of ±VSENSEB. ±1V is the largest valid input range.
starts on the positive edge.
REFLB (Pins 11, 12): Channel B Low Reference. Short
together and bypass to Pins 13, 14 with a 0.1µF ceramic
VCMB (Pin 20): Channel B 1.5V Output and Input Common
Mode Bias. Bypass to ground with 2.2µF ceramic chip
capacitor. Do not connect to VCMA.
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| Páginas | Total 28 Páginas | |
| PDF Descargar | [ Datasheet LTC2292.PDF ] | |
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