PDF CY7C1387B Data sheet ( Hoja de datos )

Número de pieza	CY7C1387B
Descripción	(CY7C1386B / CY7C1387B) 512K x 36/1M x 18 Pipelined DCD SRAM
Fabricantes	Cypress Semiconductor
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No Preview Available ! www.DataSheet4U.com 86B CY7C1386B CY7C1387B 512K x 36/1M x 18 Pipelined DCD SRAM Features registers controlled by a positive-edge-triggered Clock Input (CLK). The synchronous inputs include all addresses, data • Fast clock speed: 200, 167, 150, 133 MHz inputs, address-pipelining Chip Enables (CEs), burst control • Provide high-performance 3-1-1-1 access rate • Fast OE access times: 3.0, 3.4, 3.8, and 4.2 ns inputs (ADSC, ADSP, and ADV), Write Enables (BWa, BWb, BWc, BWd and BWE), and Global Write (GW). • Optimal for depth expansion • 3.3V (–5% / +10%) power supply • Common data inputs and data outputs • Byte Write Enable and Global Write control Asynchronous inputs include the Output Enable (OE) and burst mode control (MODE). DQa,b,c,d and DPa,b,c,d apply to CY7C1386B and DQa,b and DPa,b apply to CY7C1387B. a, b, c, and d each are 8 bits wide in the case of DQ and 1 bit wide in the case of DP. • Double-cycle deselect • Chip enable for address pipeline Addresses and chip enables are registered with either Address Status Processor (ADSP) or Address Status • Address, data, and control registers Controller (ADSC) input pins. Subsequent burst addresses • Internally self-timed Write cycle • Burst control pins (interleaved or linear burst sequence) can be internally generated as controlled by the Burst Advance Pin (ADV). Address, data inputs, and write controls are registered on-chip • Automatic power-down available using ZZ mode or CE deselect to initiate self-timed Write cycles. Write cycles can be one to four bytes wide as controlled by the write control inputs. • High-density, high-speed packages Individual byte write allows individual byte to be written. BWa • JTAG boundary scan for BGA packaging version controls DQa and DQPa. BWb controls DQb and DQPb. BWc • Automatic power down available using ZZ mode or CE deselect controls DQc and DQPd. BWd controls DQd–DQd and DQPd. BWa, BWb, BWc, and BWd can be active only with BWE LOW. Functional Description GW LOW causes all bytes to be written. Write pass-through www.DataSheceapta4bUili.tycoamllows written data available at the output for the The Cypress Synchronous Burst SRAM family employs high-speed, low-power CMOS designs using advanced single-layer polysilicon, triple-layer metal technology. Each immediately next Read cycle. This device also incorporates pipelined enable circuit for easy depth expansion without penalizing system performance. memory cell consists of six transistors. The CY7C1386B and CY7C1387B are both double-cycle The CY7C1386B and CY7C1387B SRAMs integrate deselect parts. All inputs and outputs of the CY7C1386B and 524,288 × 36 and 1,048,576 × 18 SRAM cells with advanced the CY7C1387B are JEDEC-standard JESD8-5-compatible. synchronous peripheral circuitry and a 2-bit counter for internal burst operation. All synchronous inputs are gated by Selection Guide Maximum Access Time Maximum Operating Current Maximum CMOS Standby Current 200 MHz 3 315 20 167 MHz 3.4 285 20 150 MHz 3.8 265 20 133 MHz 4.2 245 20 Unit ns mA mA Cypress Semiconductor Corporation • 3901 North First Street • San Jose • CA 95134 • 408-943-2600 Document #: 38-05195 Rev. Revised December 3, 2001 www.DataSheet4U.com 1 page www.DataSheet4U.com Pin Configurations (continued) CY7C1386B CY7C1387B 165-Ball Bump FBGA 12 A NC A B NC C DPc A NC D DQc DQc E DQc DQc F DQc DQc G DQc DQc H NC VSS J DQd DQd K DQd DQd L DQd DQd M DQd DQd N DPd NC P NC 64M R MODE 32M CY7C1386B (512K × 36) — 11 × 15 FBGA 3 CE1 CE2 VDDQ VDDQ VDDQ VDDQ VDDQ NC VDDQ VDDQ VDDQ VDDQ VDDQ A A 4 BWc BWd VSS VDD VDD VDD VDD VDD VDD VDD VDD VDD VSS A A 5 BWb BWa VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS NC TDI TMS 6 CE3 CLK VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS A A1 A0 7 BWE GW VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS NC TDO TCK 8 ADSC OE VSS VDD VDD VDD VDD VDD VDD VDD VDD VDD VSS A A 9 ADV ADSP VDDQ VDDQ VDDQ VDDQ VDDQ NC VDDQ VDDQ VDDQ VDDQ VDDQ A A 10 A A NC DQb DQb DQb DQb NC DQa DQa DQa DQa NC A A 11 NC 128M DPb DQb DQb DQb DQb ZZ DQa DQa DQa DQa DPa A A 12 A NC A B NC A C NC NC D NC DQb E NC DQb F NC DQb G NC DQb H NC J DQb VSS NC K DQb L DQb NC NC M DQb NC N DPb NC P NC 64M R MODE 32M www.DataSheet4U.com CY7C1387B (1M × 18) — 11 × 15 FBGA 3 CE1 CE2 VDDQ VDDQ VDDQ VDDQ VDDQ NC VDDQ VDDQ VDDQ VDDQ VDDQ A A 4 BWb NC VSS VDD VDD VDD VDD VDD VDD VDD VDD VDD VSS A A 5 NC BWa VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS NC TDI TMS 6 CE3 CLK VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS A A1 A0 7 BWE GW VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS NC TDO TCK 8 ADSC OE VSS VDD VDD VDD VDD VDD VDD VDD VDD VDD VSS A A 9 ADV ADSP VDDQ VDDQ VDDQ VDDQ VDDQ NC VDDQ VDDQ VDDQ VDDQ VDDQ A A 10 A A NC NC NC NC NC NC DQa DQa DQa DQa NC A A 11 A 128M DPa DQa DQa DQa DQa ZZ NC NC NC NC NC A A Document #: 38-05195 Rev. www.DataSheet4U.com Page 5 of 32 5 Page www.DataSheet4U.com Write Cycle Descriptions[5,6,7] Function (1386B) Read Read Write Byte 0 - DQa Write Byte 1- DQb Write Bytes 1, 0 Write Byte 2 - DQc Write Bytes 2, 0 Write Bytes 2, 1 Write Bytes 2, 1, 0 Write Byte 3 - DQd5 Write Bytes 3, 0 Write Bytes 3, 1 Write Bytes 3, 1, 0 Write Bytes 3, 2 Write Bytes 3, 2, 0 Write Bytes 3, 2, 1 Write All Bytes Write All Bytes CY7C1386B CY7C1387B GW BWE BWd 11X 101 101 101 101 101 101 101 101 100 100 100 100 100 100 100 www.DataSheet4U.com 100 0XX BWc X 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 X BWb X 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 X BWa X 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 X Function (1387B) Read Read Write Byte 0 - DQ[7:0] and DP0 Write Byte 1 - DQ[15:8] and DP1 Write All Bytes Write All Bytes GW BWE BWb BWa 1 1 XX 10 11 10 10 10 01 10 00 0X XX Notes: 5. X = “Don't Care”, 1 = Logic HIGH, 0 = Logic LOW. 6. The SRAM always initiates a Read cycle when ADSP asserted, regardless of the state of GW, BWE, or BWx. Writes may occur only on subsequent clocks after the ADSP or with the assertion of ADSC. As a result, OE must be driven HIGH prior to the start of the Write cycle to allow the outputs to three-state. OE is a “don't care” for the remainder of the Write cycle. 7. OE is asynchronous and is not sampled with the clock rise. It is masked internally during Write cycles. During a Read cycle DQ = High-Z when OE is inactive or when the device is deselected, and DQ = data when OE is active. Document #: 38-05195 Rev. ** www.DataSheet4U.com Page 11 of 32 11 Page

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