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PDF BUK7L11-34ARC Data sheet ( Hoja de datos )
| Número de pieza | BUK7L11-34ARC | |
| Descripción | TrenchPLUS standard level FET | |
| Fabricantes | NXP Semiconductors | |
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BUK7L11-34ARC
TrenchPLUS standard level FET
Rev. 03 — 3 December 2003
Product data
1. Product profile
1.1 Description
N-channel enhancement mode field-effect power transistor in a plastic package using
TrenchMOS™ technology, featuring very low on-state resistance, integral gate
resistor, ESD protection diodes and clamping diodes to protect the MOSFET from
avalanching.
1.2 Features
s ESD and overvoltage protection
s Internal gate resistor
s Q101 compliant
s On-state resistance 8 mΩ (typ).
1.3 Applications
s 12 V loads
s Motors, lamps and solenoids.
1.4 Quick reference data
s VDSR(CL) = 41 V (typ)
s ID ≤ 89 A
s RDSon = 8 mΩ (typ)
s Ptot ≤ 172 W.
2. Pinning information
Table 1: Pinning - SOT78C, simplified outline and symbol
Pin Description
Simplified outline
1 gate (g)
2 drain (d)
mb
3 source (s)
mb mounting base,
connected to drain (d)
123
MBL370
SOT78C (TO-220)
Symbol
g
d
s MBL521
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Philips Semiconductors
BUK7L11-34ARC
TrenchPLUS standard level FET
6. Characteristics
Table 5: Characteristics
Tj = 25 °C unless otherwise specified.
Symbol Parameter
Conditions
Static characteristics
V(BR)DG
VDSR(CL)
drain-gate zener breakdown
voltage
drain-source clamping
voltage (DC)
ID = 2 mA; VGS = 0 V
Tj = 25 °C
Tj = −55 °C
IGS(CL) = −2 mA; ID = 1 A
Figure 16 and 17
VGS(th)
gate-source threshold voltage ID = 1 mA; VDS = VGS;
Figure 9
IDSS
V(BR)GSS
IGSS
RDSon
drain-source leakage current
gate-source breakdown
voltage
gate-source leakage current
drain-source on-state
resistance
Tj = 25 °C
Tj = 175 °C
Tj = 150 °C
Tj = −55 °C
VDS = 16 V; VGS = 0 V
Tj = 25 °C
Tj = 150 °C
Tj = 175 °C
IG = ±1 mA;
−55 °C < Tj < +175 °C
VGS = ±10 V; VDS = 0 V
Tj = 25 °C
Tj = 175 °C
VGS = 16 V; VDS = 0 V
Tj = 175 °C
VGS = 10 V; ID = 30 A;
Figure 7 and 8
RG Internal gate resistor
Dynamic characteristics
Tj = 25 °C
Tj = 175 °C
VGS = 16 V; ID = 30 A
Qg(tot)
Qgs
Qgd
Ciss
Coss
Crss
total gate charge
gate-source charge
gate-drain (Miller) charge
input capacitance
output capacitance
reverse transfer capacitance
VGS = 10 V; VDS = 27 V;
ID = 25 A; Figure 14
VGS = 0 V; VDS = 25 V;
f = 1 MHz; Figure 12
Min
34
34
[1] -
2.2
1.2
1.5
-
-
-
-
20
-
-
-
-
-
-
-
-
-
-
-
-
Typ Max Unit
- 45 V
- 45 V
41 -
V
3 3.8 V
--V
--V
- 4.2 V
0.1 2
µA
3 50 µA
18 250 µA
22 -
V
5
1000
nA
- 50 µA
- 150 µA
8
-
7
11
53
11
20
1 880
640
400
11
20.9
9.7
-
-
-
-
2 506
768
548
mΩ
mΩ
mΩ
Ω
nC
nC
nC
pF
pF
pF
9397 750 12163
Product data
DataSheet4 U .com
Rev. 03 — 3 December 2003
© Koninklijke Philips Electronics N.V. 2003. All rights reserved.
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Philips Semiconductors
BUK7L11-34ARC
TrenchPLUS standard level FET
7. Package outline
Plastic single-ended package; heatsink mounted; 1 mounting hole; 3 leads
SOT78C
EA
p A1
q
mounting
base
D1
q1
D
q2
L b1
L1
Q
123
e
e1
H
b
c
0 5 10 mm
scale
DIMENSIONS (mm are the original dimensions)
UNIT A A1 b b1 c
D D1 E
e e1 H
L L1 p
Q q q1 q2
mm
4.58 1.33 0.87 1.33 0.44 15.07 6.47 10.40 2.64 5.16 6.03 14.00 6.10 3.90
4.31 1.21 0.76 1.21 0.33 14.80 6.22 10.00 2.44 5.00 5.76 13.50 5.58 3.78
2.72 2.95 3.80 12.40
2.40 2.69 3.42 12.00
Notes
1. Terminals in this zone are not tinned.
OUTLINE
VERSION
SOT78C
REFERENCES
IEC
JEDEC
JEITA
3-lead TO-220
EUROPEAN
PROJECTION
ISSUE DATE
01-12-11
03-01-21
Fig 18. SOT78C (TO-220).
9397 750 12163
Product data
DataSheet4 U .com
Rev. 03 — 3 December 2003
© Koninklijke Philips Electronics N.V. 2003. All rights reserved.
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