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PDF MC14557B Data sheet ( Hoja de datos )
| Número de pieza | MC14557B | |
| Descripción | 1-to-64 Bit Variable Length Shift Register | |
| Fabricantes | ON Semiconductor | |
| Logotipo |  |
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MC14557B
1-to-64 Bit Variable Length
Shift Register
The MC14557B is a static clocked serial shift register whose length
may be programmed to be any number of bits between 1 and 64. The
number of bits selected is equal to the sum of the subscripts of the
enabled Length Control inputs (L1, L2, L4, L8, L16, and L32) plus
one. Serial data may be selected from the A or B data inputs with the
A/B select input. This feature is useful for recirculation purposes. A
Clock Enable (CE) input is provided to allow gating of the clock or
negative edge clocking capability.
The device can be effectively used for variable digital delay lines or
simply to implement odd length shift registers.
• 1–64 Bit Programmable Length
• Q and Q Serial Buffered Outputs
• Asynchronous Master Reset
• All Inputs Buffered
• No Limit On Clock Rise and Fall Times
• Supply Voltage Range = 3.0 Vdc to 18 Vdc
• Capable of Driving Two Low–power TTL Loads or one Low–power
Schottky TTL Load Over the Rated Temperature Range
MAXIMUM RATINGS (Voltages Referenced to VSS) (Note 2.)
Symbol
Parameter
Value
Unit
VDD
Vin, Vout
DC Supply Voltage Range
Input or Output Voltage Range
(DC or Transient)
– 0.5 to +18.0
– 0.5 to VDD + 0.5
V
V
Iin, Iout
Input or Output Current
(DC or Transient) per Pin
±10 mA
PD Power Dissipation,
per Package (Note 3.)
500 mW
TA Ambient Temperature Range
Tstg Storage Temperature Range
TL Lead Temperature
(8–Second Soldering)
– 55 to +125
– 65 to +150
260
°C
°C
°C
2. Maximum Ratings are those values beyond which damage to the device
may occur.
3. Temperature Derating:
Plastic “P and D/DW” Packages: – 7.0 mW/_ C From 65_ C To 125_ C
This device contains protection circuitry to guard against damage due to high
static voltages or electric fields. However, precautions must be taken to avoid
applications of any voltage higher than maximum rated voltages to this
v vhigh–impedance circuit. For proper operation, Vin and Vout should be constrained
to the range VSS (Vin or Vout) VDD.
Unused inputs must always be tied to an appropriate logic voltage level (e.g.,
either VSS or VDD). Unused outputs must be left open.
http://onsemi.com
PDIP–16
P SUFFIX
CASE 648
MARKING
DIAGRAMS
16
MC14557BCP
AWLYYWW
1
16
SOIC–16
DW SUFFIX
CASE 751G
14557B
AWLYYWW
1
SOEIAJ–16
F SUFFIX
CASE 966
16
MC14557B
AWLYWW
1
A = Assembly Location
WL or L = Wafer Lot
YY or Y = Year
WW or W = Work Week
ORDERING INFORMATION
Device
MC14557BCP
MC14557BDW
Package
PDIP–16
SOIC–16
Shipping
2000/Box
47/Rail
MC14557BDWR2 SOIC–16 1000/Tape & Reel
MC14557BF
SOEIAJ–16 See Note 1.
MC14557BFEL SOEIAJ–16 See Note 1.
1. For ordering information on the EIAJ version of
the SOIC packages, please contact your local
ON Semiconductor representative.
© Semiconductor Components Industries, LLC, 2000
March, 2000 – Rev. 3
DataSheet4 U .com
1
Publication Order Number:
MC14557B/D
1 page  
www.DataSheet4U.com
50%
CLOCK
A INPUT
tWH(cl)
1/fcl
50%
tsu
RESET
1–bit length:
CE = 0
A/B = 1
Q
L1 = L2 = L4 = L8 = L16 = L32 = 0
tPLH
MC14557B
TIMING DIAGRAM
th
tTLH
90%
50%
10%
tTHL
tPHL
trem
50%
PWR
tPHL
VDD
VSS
VDD
VSS
VDD
VSS
VOH
VOL
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