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PDF MC74AC74 Data sheet ( Hoja de datos )
| Número de pieza | MC74AC74 | |
| Descripción | DUAL D-TYPE POSITIVE EDGE-TRIGGERED FLIP-FLOP | |
| Fabricantes | Motorola Semiconductors | |
| Logotipo |  |
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Dual DĆType Positive
EdgeĆTriggered FlipĆFlop
The MC74AC74/74ACT74 is a dual D-type flip-flop with Asynchronous Clear
and Set inputs and complementary (Q,Q) outputs. Information at the input is
transferred to the outputs on the positive edge of the clock pulse. Clock triggering
occurs at a voltage level of the clock pulse and is not directly related to the transition
time of the positive-going pulse. After the Clock Pulse input threshold voltage has
been passed, the Data input is locked out and information present will not be
transferred to the outputs until the next rising edge of the Clock Pulse input.
Asynchronous Inputs:
LOW input to SD (Set) sets Q to HIGH level
LOW input to CD (Clear) sets Q to LOW level
Clear and Set are independent of clock
Simultaneous LOW on CD and SD makes both Q and Q HIGH
• Outputs Source/Sink 24 mA
• ′ACT74 Has TTL Compatible Inputs
VCC CD2 D2 CP2 SD2 Q2
14 13 12 11 10 9
Q2
8
D1 CD1 Q1
CP1 SD1 Q1
CP2 SD2 Q2
D2 CD2 Q2
1234567
CD1 D1 CP1 SD1 Q1 Q1 GND
TRUTH TABLE (Each Half)
Inputs
Outputs
SD CD CP D Q
Q
L HXX H L
H LXX L H
L LXX H H
HH
HH
L
HH
LL
H
H H L X Q0 Q0
H = HIGH Voltage Level
L = LOW Voltage Level
X = Immaterial
= LOW-to-HIGH Clock Transition
Q0(Q0) = Previous Q(Q) before
LOW-to-HIGH Transition of Clock
PIN NAMES
D1, D2
CP1, CP2
CD1, CD2
SD1, SD2
Q1, Q1, Q2, Q2
Data Inputs
Clock Pulse Inputs
Direct Clear Inputs
Direct Set Inputs
Outputs
MC74AC74
MC74ACT74
DUAL D-TYPE POSITIVE
EDGE-TRIGGERED
FLIP-FLOP
N SUFFIX
CASE 646-06
PLASTIC
D SUFFIX
CASE 751A-03
PLASTIC
LOGIC SYMBOL
Q1 Q1
SD1 CD1
D1 CP1
Q2
SD2
D2 CP2
Q2
CD2
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FACT DATA
5-1
1 page  
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MC74AC74 MC74ACT74
AC CHARACTERISTICS (For Figures and Waveforms — See Section 3)
74ACT
Symbol
Parameter
VCC*
(V)
TA = +25°C
CL = 50 pF
fmax
Maximum Clock
Frequency
tPLH
Propagation Delay
CDn or SDn to Qn or Qn
tPHL
Propagation Delay
CDn or SDn to Qn or Qn
tPLH
Propagation Delay
CPn to Qn or Qn
tPHL
Propagation Delay
CPn to Qn or Qn
* Voltage Range 5.0 V is 5.0 V ±0.5 V.
Min Typ Max
5.0 145 210
5.0 3.0 5.5 9.5
5.0 3.0 6.0 10.0
5.0 4.0 7.5 11.0
5.0 3.5 6.0 10.0
74ACT
TA = –40°C
to +85°C
CL = 50 pF
Min Max
125
2.5 10.5
3.0 11.5
4.0 13.0
3.0 11.5
Unit
MHz
ns
ns
ns
ns
Fig.
No.
3-3
3-6
3-6
3-6
3-6
AC OPERATING REQUIREMENTS
Symbol
Parameter
ts
Set-up Time, HIGH or LOW
Dn to CPn
th
Hold Time, HIGH or LOW
Dn to CPn
tw
CPn or CDn or SDn
Pulse Width
trec
Recovery TIme
CDn or SDn to CP
* Voltage Range 5.0 V is 5.0 V ±0.5 V.
74ACT
74ACT
VCC*
(V)
TA = +25°C
CL = 50 pF
TA = –40°C
to +85°C
CL = 50 pF
Unit
Fig.
No.
Typ Guaranteed Minimum
5.0 1.0
3.0
3.5 ns 3-9
5.0 –0.5
1.0
1.0 ns 3-9
5.0 3.0
5.0
6.0 ns 3-6
5.0 –2.5
0
0 ns 3-9
CAPACITANCE
Symbol
Parameter
CIN
CPD
Input Capacitance
Power Dissipation Capacitance
Value
Typ
4.5
35
Unit
pF
pF
Test Conditions
VCC = 5.0 V
VCC = 5.0 V
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FACT DATA
5-5
5 Page | ||
| Páginas | Total 6 Páginas | |
| PDF Descargar | [ Datasheet MC74AC74.PDF ] | |
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