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부품번호 | ICS9DB202 기능 |
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기능 | Two 0.7V current mode differential HCSL output pairs | ||
제조업체 | Integrated Circuit Systems | ||
로고 | |||
전체 11 페이지수
www.DataSheet4U.com
Integrated
Circuit
Systems, Inc.
ICS9DB202
PCI EXPRESS™
JITTER ATTENUATOR
GENERAL DESCRIPTION
The ICS9DB202 is a high perfromance 1-to-2 Dif-
ICS ferential-to-HCSL Jitter Attenuator designed for use
HiPerClockS™ in PCI Express™ systems. In some PCI Express™
systems, such as those found in desktop PCs, the
PCI Express™ clocks are generated from a low
bandwidth, high phase noise PLL frequency synthesizer. In these
systems, a jitter-attenuating device may be necessary in order
to reduce high frequency random and deterministic jitter com-
ponents from the PLL synthesizer and from the system board.
The ICS9DB202 has two PLL bandwidth modes. In low band-
width mode, the PLL loop bandwidth is 500kHz.This setting of-
fers the best jitter attenuation and is still high enough to pass a
triangular input spread spectrum profile. In high bandwidth mode,
the PLL bandwidth is at 1MHz and allows the PLL to pass more
spread spectrum modulation.
For serdes which have x10 reference multipliers instead of x12.5
multipliers, each of the two PCI Express™ outputs (PCIEX0:1)
can be set for 125MHz instead of 100MHz by configuring the
appropriate frequency select pins (FS0:1).
BLOCK DIAGRAM
IREF
+-
Current
Set
nOE0
1 HiZ
0 Enabled
nCLK
CLK
Phase
Detector
Loop
Filter
VCO
÷5
Internal Feedback
Features
• Two 0.7V current mode differential HCSL output pairs
• 1 differential clock input
• CLK and nCLK supports the following input types:
LVPECL, LVDS, LVHSTL, SSTL, HCSL
• Maximum output frequency: 140MHz
• Output skew: 110ps (maximum)
• Cycle-to-cycle jitter: 110ps (maximum)
• RMS phase jitter @ 100MHz, (1.5MHz - 22MHz):
2.42ps (typical)
• 3.3V operating supply
• 0°C to 70°C ambient operating temperature
• Lead-Free package available
• Industrial temperature information available upon request
PIN ASSIGNMENT
0
0 ÷4
1 ÷5 1
FS0
0 ÷5
1 ÷4
0
1
PLL_BW 1
2 0 VDDA
CLK 2 19 BYPASS
nCLK 3 18 IREF
FS0 4 17 FS1
VDD 5
16 VDD
GND 6 15 GND
PCIEXT0 7 14 PCIEXT1
PCIEXC0 8 13 PCIEXC1
VDD 9
12 VDD
nOE0 10 11 nOE1
ICS9DB202
20-Lead TSSOP
6.50mm x 4.40mm x 0.92
PCIEXT0
nPCIEXC0
package body
G Package
Top View
ICS9DB202
20-Lead, 209-MIL SSOP
5.30mm x 7.20mm x 1.75mm
body package
F Package
Top View
PCIEXT1
nPCIEXC1
BYPASS
nOE1
1 HiZ
0 Enabled
FS1
9DB202CG
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1
REV. A OCTOBER 6, 2004
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Integrated
Circuit
Systems, Inc.
ICS9DB202
PCI EXPRESS™
JITTER ATTENUATOR
TABLE 4D. HCSL DC CHARACTERISTICS, VDD = VDDA = 3.3V±5%, TA = 0°C TO 70°C, RREF = 475Ω
Symbol Parameter
Test Conditions
Minimum Typical
IOH Output Current
VOH Output High Voltage
VOL Output Low Voltage
IOZ High Impedance Leakage Current
VOX Output Crossover Voltage
12 14
680
-10
250
Maximum
16
65
10
550
Units
mA
V
V
µA
mV
TABLE 5. AC CHARACTERISTICS, VDD = VDDA = 3.3V±5%, TA = 0°C TO 70°C, RREF = 475Ω
Symbol Parameter
Test Conditions
Minimum Typical Maximum Units
fMAX
tsk(o)
Output Frequency
Output Skew; NOTE 1, 2
50
tjit(cc) Cycle-to-Cycle Jitter
Outputs @ Different Frequencies
Outputs @ Same Frequencies
tjit(Ø)
RMS Phase Jitter
(Random); NOTE 3
Integration Range: 1.5MHz - 22MHz
2.42
tR / tF
odc
Output Rise/Fall Time
Output Duty Cycle
20% to 80%
300
48
NOTE 1: Defined as skew between outputs at the same supply voltage and with equal load conditions.
Measured at the output differential cross points.
NOTE 2: This parameter is defined in accordance with JEDEC Standard 65.
NOTE 3: Please refer to the Phase Noise Plot following this section.
140
110
110
50
1100
52
MHz
ps
ps
ps
ps
ps
%
9DB202CG
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REV. A OCTOBER 6, 2004
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Integrated
Circuit
Systems, Inc.
APPLICATION INFORMATION
ICS9DB202
PCI EXPRESS™
JITTER ATTENUATOR
POWER SUPPLY FILTERING TECHNIQUES
As in any high speed analog circuitry, the power supply pins are
vulnerable to random noise.The ICS9DB202 provides separate
power supplies to isolate any high switching noise from the out-
puts to the internal PLL.V and V should be individually con-
DD DDA
nected to the power supply plane through vias, and bypass ca-
pacitors should be used for each pin. To achieve optimum jitter
performance, power supply isolation is required. Figure 1 illus-
trates how a 24Ω resistor along with a 10µF and a .01µF by-
pass capacitor should be connected to each VDDA pin.
V
DD
VDDA
3.3V
.01µF 24Ω
.01µF
10µF
FIGURE 1. POWER SUPPLY FILTERING
WIRING THE DIFFERENTIAL INPUT TO ACCEPT SINGLE ENDED LEVELS
Figure 2 shows how the differential input can be wired to accept
single ended levels. The reference voltage V_REF = VDD/2 is
generated by the bias resistors R1, R2 and C1. This bias circuit
should be located as close as possible to the input pin.The ratio
of R1 and R2 might need to be adjusted to position the V_REF in
the center of the input voltage swing. For example, if the input
clock swing is only 2.5V and VDD = 3.3V, V_REF should be 1.25V
and R2/R1 = 0.609.
VDD
Single Ended Clock Input
V_REF
C1
0.1u
R1
1K
CLK
nCLK
R2
1K
9DB202CG
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FIGURE 2. SINGLE ENDED SIGNAL DRIVING DIFFERENTIAL INPUT
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REV. A OCTOBER 6, 2004
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부품번호 | 상세설명 및 기능 | 제조사 |
ICS9DB202 | Two 0.7V current mode differential HCSL output pairs | Integrated Circuit Systems |
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