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AD7142 데이터시트 PDF




Analog Devices에서 제조한 전자 부품 AD7142은 전자 산업 및 응용 분야에서
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부품번호 AD7142 기능
기능 Programmable Controller
제조업체 Analog Devices
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AD7142 데이터시트, 핀배열, 회로
FEATURES
Programmable capacitance-to-digital converter
36 ms update rate (@ maximum sequence length)
Better than 1 fF resolution
14 capacitance sensor input channels
No external RC tuning components required
Automatic conversion sequencer
On-chip automatic calibration logic
Automatic compensation for environmental changes
Automatic adaptive threshold and sensitivity levels
On-chip RAM to store calibration data
SPI®-compatible serial interface (AD7142)
I2C®-compatible serial interface (AD7142-1)
Separate VDRIVE level for serial interface
Interrupt output and GPIO
32-lead, 5 mm x 5 mm LFCSP_VQ
2.6 V to 3.6 V supply voltage
Low operating current
Full power mode: less than 1 mA
Low power mode: 50 μA
APPLICATIONS
Personal music and multimedia players
Cell phones
Digital still cameras
Smart hand-held devices
Television, A/V, and remote controls
Gaming consoles
GENERAL DESCRIPTION
The AD7142 and AD7142-1 are integrated capacitance-to-
digital converters (CDCs) with on-chip environmental
calibration for use in systems requiring a novel user input
method. The AD7142 and AD7142-1 can interface to external
capacitance sensors implementing functions such as capacitive
buttons, scroll bars, or wheels.
The CDC has 14 inputs channeled through a switch matrix to a
16-bit, 250 kHz sigma-delta (∑-Δ) capacitance-to-digital
converter. The CDC is capable of sensing changes in the
capacitance of the external sensors and uses this information to
register a sensor activation. The external sensors can be
arranged as a series of buttons, as a scroll bar or wheel, or as a
combination of sensor types. By programming the registers, the
user has full control over the CDC setup. High resolution
sensors require minor software to run on the host processor.
Rev. A
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarksandregisteredtrademarksarethepropertyoftheirrespectiveowners.
Programmable Controller for
Capacitance Touch Sensors
AD7142
CIN0
CIN1
CIN2
CIN3
CIN4
CIN5
CIN6
CIN7
CIN8
CIN9
CIN10
CIN11
CIN12
CIN13
30
31
32
1
2
3
4
5
6
7
8
9
10
11
FUNCTIONAL BLOCK DIAGRAM
VREF– VREF+
29 28
TEST
27
POWER-ON
RESET
LOGIC
16-BIT
Σ-Δ
CDC
CALIBRATION
ENGINE
CONTROL
AND
DATA
REGISTERS
CALIBRATION
RAM
13 AVCC
14 AGND
17 DVCC
18 DGND1
19 DGND2
CSHIELD 12
SRC 15
SRC 16
250kHz
EXCITATION
SOURCE
VDRIVE 20
SERIAL INTERFACE
AND CONTROL LOGIC
INTERRUPT
AND GPIO
LOGIC
26 GPIO
21
SDO/
SDA
22 23 24
SDI/
ADD0
SCLK
CS/
ADD1
Figure 1.
25
INT
The AD7142 and AD7142-1 have on-chip calibration logic to
account for changes in the ambient environment. The calibration
sequence is performed automatically and at continuous intervals,
when the sensors are not touched. This ensures that there are no
false or nonregistering touches on the external sensors due to a
changing environment.
The AD7142 has an SPI-compatible serial interface, and the
AD7142-1 has an I2C-compatible serial interface. Both parts
have an interrupt output, as well as a general-purpose input/
output (GPIO).
The AD7142 and AD7142-1 are available in a 32-lead, 5 mm ×
5 mm LFCSP_VQ and operate from a 2.6 V to 3.6 V supply. The
operating current consumption is less than 1 mA, falling to
50 μA in low power mode (conversion interval of 400 ms).
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
www.analog.com
Fax: 781.461.3113
©2007 Analog Devices, Inc. All rights reserved.




AD7142 pdf, 반도체, 판매, 대치품
AD7142
SPECIFICATIONS
AVCC, DVCC = 2.6 V to 3.6 V, TA = −40oC to +85°C, unless otherwise noted.
Table 1.
Parameter
CAPACITANCE-TO-DIGITAL CONVERTER
Update Rate
Resolution
CIN Input Range1
No Missing Codes
CIN Input Leakage
Total Unadjusted Error
Output Noise (Peak-to-Peak)
Min
35.45
16
Output Noise (RMS)
Parasitic Capacitance
CBULK Offset Range1
CBULK Offset Resolution
Low Power Mode Delay Accuracy
EXCITATION SOURCE
Frequency
Output Voltage
Short-Circuit Source Current
Short-Circuit Sink Current
Maximum Output Load
CSHIELD Output Drive
CSHIELD Bias Level
LOGIC INPUTS (SDI, SCLK, CS, SDA, GPI TEST)
VIH Input High Voltage
VIL Input Low Voltage
IIH Input High Voltage
IIL Input Low Voltage
Hysteresis
OPEN-DRAIN OUTPUTS (SCLK, SDA, INT)
VOL Output Low Voltage
IOH Output High Leakage Current
LOGIC OUTPUTS (SDO, GPO)
VOL Output Low Voltage
VOH Output High Voltage
SDO Floating State Leakage Current
GPO Floating State Leakage Current
POWER
AVCC, DVCC
VDRIVE
ICC
240
0.7 × VDRIVE
−1
VDRIVE − 0.6
−5
2.6
1.65
Typ
36.86
16
±2
25
7
3
0.8
0.5
±20
156.25
250
20
50
250
10
AVCC/2
150
0.1
3.3
0.9
16
2.25
Max Unit Test Conditions/Comments
38.4 ms 12 conversion stages in sequencer, decimation rate = 256
Bit
pF
Bit Guaranteed by design, but not production tested
nA
±20 %
Codes Decimation rate = 128
Codes Decimation rate = 256
Codes Decimation rate = 128
Codes Decimation rate = 256
40 pF
Parasitic capacitance to ground, per CIN input
guaranteed by characterization
pF
fF
4%
% of 200 ms, 400 ms, 600 ms, or 800 ms
260 kHz
AVCC V
mA
mA
pF
μA
V
Capacitance load on source to ground
V
0.4 V
μA
1 μA
mV
VIN = VDRIVE
VIN = DGND
0.4 V
±1 μA
ISINK = −1 mA
VOUT = VDRIVE
0.4 V
V
±1 μA
2 μA
3.6 V
3.6 V
1 mA
20 μA
33 μA
4.5 μA
18 μA
ISINK = 1 mA, VDRIVE = 1.65 V to 3.6 V
ISOURCE = 1 mA, VDRIVE = 1.65 V to 3.6 V
Pin three-state, leakage measured to GND and DVCC
Pin three-state, leakage measured to GND and DVCC
Serial interface operating voltage
In full power mode
Low power mode, converter idle, TA = 25°C
Low power mode, converter idle
Full shutdown, TA = 25°C
Full shutdown
1 CIN and CBULK are defined in Figure 2.
Rev. A | Page 4 of 72

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AD7142 전자부품, 판매, 대치품
AD7142
I2C TIMING SPECIFICATIONS (AD7142-1)
TA = −40°C to +85°C; VDRIVE = 1.65 V to 3.6 V; AVCC, DVCC = 2.6 V to 3.6 V, unless otherwise noted. Sample tested at 25°C to ensure
compliance. All input signals timed from a voltage level of 1.6 V.
Table 5. I2C Timing Specifications1
Parameter
Limit
fSCLK 400
t1 0.6
t2 1.3
t3 0.6
t4 100
t5 300
t6 0.6
t7 0.6
t8 1.3
tR 300
tF 300
Unit
kHz max
μs min
μs min
μs min
ns min
ns min
μs min
μs min
μs min
ns max
ns max
Description
Start condition hold time, tHD; STA
Clock low period, tLOW
Clock high period, tHIGH
Data setup time, tSU; DAT
Data hold time, tHD; DAT
Stop condition setup time, tSU; STO
Start condition setup time, tSU; STA
Bus free time between stop and start conditions, tBUF
Clock/data rise time
Clock/data fall time
1 Guaranteed by design, not production tested.
SCLK
t2 tR
t1
t5
SDATA
t8
STOP START
tF
t3
t4
t1
t7
START
Figure 4. I2C Detailed Timing Diagram
t6
STOP
Rev. A | Page 7 of 72

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