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Analog Devices에서 제조한 전자 부품 AD9380은 전자 산업 및 응용 분야에서
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부품번호 AD9380 기능
기능 Analog/HDMI Dual-Display Interface
제조업체 Analog Devices
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AD9380 데이터시트, 핀배열, 회로
www.DataSheet4U.com
FEATURES
Internal key storage for HDCP
Analog/HDMI dual interface
Supports high bandwidth digital content protection
RGB-to-YCbCr 2-way color conversion
Automated clamping level adjustment
1.8 V/3.3 V power supply
100-lead, Pb-free LQFP
RGB and YCbCr output formats
Analog interface
8-bit triple ADC
100 MSPS maximum conversion rate
Macrovision® detection
2:1 input mux
Full sync processing
Sync detect for hot plugging
Midscale clamping
Digital video interface
HDMI 1.1, DVI 1.0
150 MHz HDMI receiver
Supports HDCP 1.1
Digital audio interface
HDMI 1.1-compatible audio interface
S/PDIF (IEC90658-compatible) digital audio output
Multichannel I2S audio output (up to 8 channels)
APPLICATIONS
Advanced TVs
HDTV
Projectors
LCD monitor
GENERAL DESCRIPTION
The AD9380 offers designers the flexibility of an analog
interface and high definition multimedia interface (HDMI)
receiver integrated on a single chip. Also included is support for
high bandwidth digital content protection (HDCP).
The AD9380 is a complete 8-bit, 150 MSPS, monolithic analog
interface optimized for capturing component video (YPbPr)
and RGB graphics signals. Its 150 MSPS encode rate capability
and full power analog bandwidth of 330 MHz supports all
HDTV formats (up to 1080p and FPD resolutions up to SXGA
(1280 × 1024 @ 75 Hz).
The analog interface includes a 150 MHz triple ADC with
internal 1.25 V reference, a phase-locked loop (PLL), and
programmable gain, offset, and clamp control. The user provides
only 1.8 V and 3.3 V power supplies, analog input, and HSYNC .
Three-state CMOS outputs can be powered from 1.8 V to 3.3 V.
An on-chip PLL generates a pixel clock from HSYNC.
Rev. 0
Information furnished by Analog Devices is believed to be accurate and reliable.
However, no responsibility is assumed by Analog Devices for its use, nor for any
infringements of patents or other rights of third parties that may result from its use.
Specifications subject to change without notice. No license is granted by implication
or otherwise under any patent or patent rights of Analog Devices. Trademarks and
registered trademarks are the property of their respective owners.
DataSheet4 U .com
Analog/HDMI
Dual-Display Interface
AD9380
FUNCTIONAL BLOCK DIAGRAM
R/G/B OR YPbPrIN0
R/G/B OR YPbPrIN1
HSYNC 0
HSYNC 1
HSYNC 0
HSYNC 1
SOGIN 0
SOGIN 1
COAST
FILT
CKINV
CKEXT
SCL
SDA
Rx0+
Rx0–
Rx1+
Rx1–
Rx2+
Rx2–
RxC+
RxC–
RTERM
DDCSDA
DDCSCL
ANALOG INTERFACE
2:1
MUX
CLAMP
R/G/B 8 × 3
A/D
OR YCbCr
2:1
MUX
2:1
MUX
2:1
MUX
SYNC
PROCESSING
AND
CLOCK
GENERATION
2 DATACK
HSOUT
VSOUT
SOGOUT
REFOUT
REFIN
REF
SERIAL REGISTER
AND
POWER MANAGEMENT
DIGITAL INTERFACE
HDMI RECEIVER
R/G/B 8 × 3
OR YCbCr
2 DATACK
DE
HSYNC
VSYNC
4
HDCP
HDCP KEYS
Figure 1.
R/G/B 8 × 3
YCbCr (4:2:2
OR 4:4:4)
2 DATACK
HSOUT
VSOUT
SOGOUT
DE
S/PDIF
8-CHANNEL
I2S
SCLK
MCLK
LRCLK
AD9380
Pixel clock output frequencies range from 12 MHz to 150 MHz.
PLL clock jitter is typically less than 700 ps p-p at 150 MHz.
The AD9380 also offers full sync processing for composite sync
and sync-on-green (SOG) applications.
The AD9380 contains an HDMI 1.1-compatible receiver and
supports all HDTV formats (up to 1080p and 720p) and display
resolutions up to SXGA (1280 × 1024 @ 75 Hz). The receiver
features an intrapair skew tolerance of up to one full clock cycle.
With the inclusion of HDCP, displays can now receive
encrypted video content. The AD9380 allows for authentication
of a video receiver, decryption of encoded data at the receiver,
and renewability of the authentication during transmission, as
specified by the HDCP 1.1 protocol.
Fabricated in an advanced CMOS process, the AD9380 is
provided in a space-saving, 100-lead, surface-mount, Pb-free
plastic LQFP and is specified over the 0°C to 70°C temperature
range.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
www.analog.com
Fax: 781.461.3113 © 2005 Analog Devices, Inc. All rights reserved.




AD9380 pdf, 반도체, 판매, 대치품
www.DataSheet4U.com
AD9380
Parameter
POWER SUPPLY
VD Supply Voltage
DVDD Supply Voltage
VDD Supply Voltage
PVDD Supply Voltage
ID Supply Current (VD)
IDVDD Supply Current (DVDD)
IDD Supply Current (VDD)2
IPVDD Supply Current (PVDD)
Total Power
Power-Down Dissipation
DYNAMIC PERFORMANCE
Analog Bandwidth,
Full Power
Signal–to–Noise Ratio (SNR)
Without Harmonics
fIN = 40.7 MHz
Crosstalk
THERMAL CHARACTERISTICS
θJA Junction-to-Ambient
AD9380KSTZ-100
Temp Test Level Min
Typ Max
Full IV 3.15
Full IV 1.7
Full IV 1.7
Full IV 1.7
25°C VI
25°C VI
25°C VI
25°C VI
Full VI
Full VI
3.3 3.47
1.8 1.9
3.3 3.47
1.8 1.9
260 300
45 60
37 1003
10 15
1.1 1.4
130
25°C V
25°C I
Full V
Full V
V
330
46
45
60
35
1 Drive strength = high.
2 DATACK load = 15 pF, data load = 5 pF.
3 Specified current and power values with a worst-case pattern (on/off).
AD9380KSTZ-150
Min Typ Max
3.15 3.3 3.47
1.7 1.8 1.9
1.7 3.3 3.47
1.7 1.8 1.9
330
85
1303
20
1.15 1.4
130
330
46
45
60
35
Unit
V
V
V
V
mA
mA
mA
mA
W
mW
MHz
dB
dB
dBc
°C/W
DIGITAL INTERFACE ELECTRICAL CHARACTERISTICS
VDD = VD =3.3 V, DVDD = PVDD = 1.8 V, ADC clock = maximum.
Table 2.
Parameter
RESOLUTION
DC DIGITAL I/O SPECIFICATIONS
High-Level Input Voltage (VIH)
Low-Level Input Voltage (VIL)
High-Level Output Voltage (VOH)
Low-Level Output Voltage (VOL)
DC SPECIFICATIONS
Output High Level
IOHD (VOUT = VOH)
Output Low Level
IOLD (VOUT = VOL)
DATACK High Level
VOHC (VOUT = VOH)
DATACK Low Level
VOLC (VOUT = VOL)
Differential Input Voltage, Single-
Ended Amplitude
Test
Level Conditions
VI
VI
VI
VI
IV Output drive = high
IV Output drive = low
IV Output drive = high
IV Output drive = low
IV Output drive = high
IV Output drive = low
IV Output drive = high
IV Output drive = low
IV
AD9380KSTZ-100 AD9380KSTZ-150
Min Typ Max Min Typ Max Unit
8 8 Bit
2.5
VDD − 0.1
VDD − 0.1
2.5
0.8
0.1
V
0.8 V
V
0.1 V
36 36 mA
24 24 mA
12 12 mA
8 8 mA
40 40 mA
20 20 mA
30 30 mA
15 15 mA
75
700 75
700 mV
DataSheet4 U .com
Rev. 0 | Page 4 of 60

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AD9380 전자부품, 판매, 대치품
www.DataSheet4U.com
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
AD9380
GND
GREEN 7
GREEN 6
GREEN 5
GREEN 4
GREEN 3
GREEN 2
GREEN 1
GREEN 0
VDD
GND
BLUE 7
BLUE 6
BLUE 5
BLUE 4
BLUE 3
BLUE 2
BLUE 1
BLUE 0
MCLKIN
MCLKOUT
SCLK
LRCLK
I2S3
I2S2
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
PIN 1
AD9380
TOP VIEW
(Not to Scale)
75 GND
74 GAIN0
73 SOGIN 0
72 VD
71 GAIN1
70 SOGIN 1
69 GND
68 BAIN0
67 VD
66 BAIN1
65 GND
64 HSYNC 0
63 HSYNC 1
62 EXTCLK/COAST
61 VSYNC 0
60 VSYNC 1
59 PVDD
58 GND
57 FILT
56 PVDD
55 GND
54 PVDD
53 ALGND
52 PU1
51 PU2
Table 5. Complete Pinout List
Pin Type
Pin No.
INPUTS
79
77
74
71
68
66
64
63
61
60
73
70
62
62
81
Figure 2. Pin Configuration
Mnemonic
RAIN0
RAIN1
GAIN0
GAIN1
BBAIN0
BBAIN1
HSYNC 0
HSYNC 1
VSYNC 0
VSYNC 1
SOGIN 0
SOGIN 1
EXTCLK
COAST
PWRDN
Function
Analog Input for Converter R Channel 0
Analog Input for Converter R Channel 1
Analog Input for Converter G Channel 0
Analog Input for Converter G Channel 1
Analog Input for Converter B Channel 0
Analog Input for Converter B Channel 1
Horizontal SYNC Input for Channel 0
Horizontal SYNC Input for Channel 1
Vertical SYNC Input for Channel 0
Vertical SYNC Input for Channel 1
Input for Sync-on-Green Channel 0
Input for Sync-on-Green Channel 1
External Clock Input—Shares Pin with COAST
PLL COAST Signal Input—Shares Pin with EXTCLK
Power-Down Control
DataSheet4 U .com
Rev. 0 | Page 7 of 60
Value
0.0 V to 1.0 V
0.0 V to 1.0 V
0.0 V to 1.0 V
0.0 V to 1.0 V
0.0 V to 1.0 V
0.0 V to 1.0 V
3.3 V CMOS
3.3 V CMOS
3.3 V CMOS
3.3 V CMOS
0.0 V to 1.0 V
0.0 V to 1.0 V
3.3 V CMOS
3.3 V CMOS
3.3 V CMOS

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