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PDF MTV118 Data sheet ( Hoja de datos )
| Número de pieza | MTV118 | |
| Descripción | On-Screen-Display | |
| Fabricantes | Myson | |
| Logotipo |  |
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MYSON
MTV118
TECHNOLOGY
On-Screen-Display for LCD Monitor
FEATURES
• Horizontal sync input may be up to 120 KHz.
• Acceptable wide-range pixel clock up to 96MHz
from XIN pin.
• Full-screen display consists of 15 (rows) by 30 (col-
umns) characters.
• 12 x 18 dot matrix per character.
• Total of 256 characters and graphic fonts including
248 mask ROM fonts and 8 programmable RAM
fonts.
• 8 color selection maximum per display character.
• Double character height and/or width control.
• Programmable positioning for display screen cen-
ter.
• Bordering, shadowing and blinking effect.
• Programmable vertical character height (18 to 71
lines) control.
• Row to row spacing register to manipulate the con-
stant display height.
• 4 programmable background windows with multi-
level operation.
• Software clears for display frame.
• Half tone and fast blanking output.
• 8-channel/8-bit PWM D/A converter output.
• Compatible with SPI bus or I2C interface with
address 7AH (slave address is mask option).
• 16 or 24-pin PDIP/SOP package.
BLOCK DIAGRAM
GENERAL DESCRIPTION
MTV118 is designed for LCD monitor appli-
cations to display the built-in characters or fonts
onto an LCD monitor screen. The display oper-
ates by transferring data and control information
from the micro controller to the RAM through a
serial data interface. It can execute full screen
displays automatically and specific functions such
as character bordering, shadowing, blinking, dou-
ble height and width, font by font color control,
frame positioning, frame size control by character
height and windowing effect. Moreover, MTV118
also provides 8 PWM DAC channels with 8-bit
resolution and a PWM clock output for external
digital-to-analog control.
SSB
SCK
SDA
VFLB
HFLB
NC
XIN
PWM0
PWM1
PWM2
PWM3
PWM4
PWM5
PWM6
PWM7
SERIAL DATA
INTERFACE
8DATA
9ROW, COL
ACK
ARWDB
HDREN
VDREN
NROW
ADDRESS BUS
ADMINISTRATOR
5 RCADDR
9 DADDR
9 FONTADDR
5 WINADDR
5 PWMADDR
VSP CH 7
CHS
VERTD 8
VERTICAL
DISPLAY
CONTROL
5 LPN
NROW
VDREN
HORIZONTAL
ARWDB
HSP HORD 8 DISPLAY CONTROL HDREN
CLOCK
GENERATOR
VCLKX
PWM D/A
CONVERTER
8 DATA
DATA 8
CWS
CHS
DISPLAY & ROW
CONTROL
REGISTERS
LUMAR
LUMAG
LUMAB
BLINK
8 CRADDR
DATA 8
LPN 5
CWS
VCLKS
CHARACTER ROM LUMA
USER FONT RAM
BORDER
LUMINANCE &
BORDGER
GENERATOR
DATA 8
8 VERTD
8 HORD
7 CH
WINDOWS &
FRAME
CONTROL
BSEN
SHADOW
OSDENB
HSP
VSP
LUMAR
LUMAG
LUMAB
BLINK
VCLKX
COLOR
ENCODER
POWER ON
PRB
RESET
VDD
VSS
VDDA
VSSA
ROUT
GOUT
BOUT
FBKG
HTONE
This datasheet contains new product information. Myson Technology reserves the rights to modify the product specification
without notice. No liability is assumed as a result of the use of this product. No rights under any patent accompany the sales of
the product.
1/15
MTV118 Revision 2.0 01/01/1999
DataSheet4 U .com
1 page  
www.DataSheet4U.com
MYSON
TECHNOLOGY
MTV118
TABLE 1. Configuration of Transmission Formats
Address b7 b6 b5 b4 b3 b2 b1 b0 Format
Address Row 1 0 0 x R3 R2 R1 R0 a,b,c
Bytes of Columnab 0 0 x C4 C3 C2 C1 C0 a,b
Display
Reg.
Columnc
0
1
x C4 C3 C2 C1 C0
c
Attribute Row 1 0 1 x R3 R2 R1 R0 a,b,c
Bytes of Columnab 0 0 x C4 C3 C2 C1 C0 a,b
Display
Reg.
Columnc
0
1
x C4 C3 C2 C1 C0
c
User
Fonts
RAM
Row
Columnab
Columnc
1
0
0
1 x x x R2 R1 R0 a,b,c
0 C5 C4 C3 C2 C1 C0
a,b
1 C5 C4 C3 C2 C1 C0
c
The data transmission is permitted to change from format (a) to format (b) and (c), or from format (b) to
format (a), but not from format (c) back to format (a) and (b). The alternation between transmission for-
mats is configured as the state diagram shown in Figure 3 on page 5.
0, X
Initiate
Input = b7, b6
1, X
format (a)
1, X ROW
format (c) 0, 1
COL
c
0, 1
format (b)
0, 0
COL
ab
1, X
X, X DA
c
DA
ab
FIGURE 3. Transmission State Diagram
3.2 Address Bus Administrator
The administrator manages bus address arbitration of internal registers or user font RAM during exter-
nal data write-in. The external data write through serial data interface to registers must be synchronized
by internal display timing. In addition, the administrator also provides automatic incrementation to the
address bus when external writing occurs using format (c).
3.3 Vertical Display Control
The vertical display control can generate different vertical display sizes for most display standards in
current monitors. The vertical display size is calculated with the information of a double character height
bit(CHS) and a vertical display height control register(CH6-CH0).The algorithms of a repeating charac-
ter line display are shown in Tables 2 and 3. The programmable vertical size range is 270 lines to max-
imum 2130 lines.
5/15
MTV118 Revision 2.0 01/01/1999
DataSheet4 U .com
5 Page 
www.DataSheet4U.com
MYSON
TECHNOLOGY
MTV118
= 0 ⇒ Accepts negative polarity Hsync input.
VSP - = 1 ⇒ Accepts positive polarity Vsync input.
= 0 ⇒ Accepts negative polarity Vsync input.
PWM1, PWM0 - Selects the PWMCK output frequency.
= (0, 0) ⇒ XIN frequency /8
= (0, 1) ⇒ XIN frequency /4
= (1, 0) ⇒ XIN frequency /2
= (1, 1) ⇒ XIN frequency /1
The initial value is 0, 0 after power-up.
Notes : When XIN is not present, don't write data in any address. If data is written in any address, a
malfunction may occur.
TABLE 4. PWMCK Frequency and PWMDA Sampling Rate
(PWM1, PWM0)
( 0, 0 )
( 0, 1 )
( 1, 0 )
( 1 ,1 )
PWMCK Freq.
XIN frequency /8
XIN frequency /4
XIN frequency /2
XIN frequency /1
PWMDA sampling rate
XIN frequency /(8 * 256)
XIN frequency /(4 * 256)
XIN frequency /(2 * 256)
XIN frequency /(1 * 256)
3.10 PWM D/A Converter
There are 8 open-drain PWM D/A outputs (PWM0 to PWM7). The PWM D/A converter output pulse
width is programmable by writing data to columns 19-26 registers of row 15 with 8-bit resolution to con-
trol the pulse width duration from 0/256 to 255/256. The sampling rate is selected by PWM1, PWM0 as
shown in table 4. In applications, all open-drain output pins should be pulled up by external resistors to
supply voltage (5V to 9V) for the desired output range.
ROW 15
b7 b6 b5 b4 b3 b2 b1 b0
Column 19
PWMDA0
||
Column 26
PWMDA7
MSB
LSB
PWMDA0 - PWMDA7 - Defines the output pulse width of pins PWM0 to PWM7.
3.11 Color Encoder
The decoder generates the video output to ROUT, GOUT and BOUT by integrating window color, bor-
der blackedge, luminance output and color selection output (R, G, B) to form the desired video outputs.
4.0 ABSOLUTE MAXIMUM RATINGS
DC Supply Voltage(VDD,VDDA)
Ground Voltage
Storage Temperature
Ambient Operating Temperature
-0.3 to +7 V
-0.3 to VDD+0.3 V
-65 to +150 oC
0 to +70 oC
11/15
MTV118 Revision 2.0 01/01/1999
DataSheet4 U .com
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| Páginas | Total 30 Páginas | |
| PDF Descargar | [ Datasheet MTV118.PDF ] | |
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