PDF CY7C09089 Data sheet ( Hoja de datos )

Número de pieza	CY7C09089
Descripción	(CY7C09xx9) 64K/128K x 8/9 Synchronous Dual-Port Static RAM
Fabricantes	Cypress Semiconductor
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No Preview Available ! www.DataSheet4U.com 25/0251 CY7C09089/99 CY7C09189/99 64K/128K x 8/9 Synchronous Dual-Port Static RAM Features • True dual-ported memory cells which allow simulta- neous access of the same memory location • Six Flow-Through/Pipelined devices — 64K x 8/9 organizations (CY7C09089/189) — 128K x 8/9 organizations (CY7C09099/199) • Three Modes — Flow-Through — Pipelined — Burst • Pipelined output mode on both ports allows fast 100- MHz cycle time • 0.35-micron CMOS for optimum speed/power • High-speed clock to data access 6.5[1]/7.5/9/12 ns (max.) • Low operating power — Active = 195 mA (typical) — Standby = 0.05 mA (typical) • Fully synchronous interface for easier operation • Burst counters increment addresses internally — Shorten cycle times — Minimize bus noise — Supported in Flow-Through and Pipelined modes • Dual Chip Enables for easy depth expansion • Automatic power-down • Commercial and Industrial temperature ranges • Available in 100-pin TQFP • Pin-compatible and functionally equivalent to IDT70908 and IDT709089 Logic Block Diagram R/WL OEL R/WR OER CE0L CE1L 1 0 0/1 1 CE0R 0 CE1R 0/1 FT/PipeL [2] I/O0L–I/O7/8L 1 0/1 8/9 0 [3] A0–A15/16L CLKL ADSL CNTENL CNTRSTL 16/17 Counter/ Address Register Decode I/O Control I/O Control True Dual-Ported RAM Array 01 0/1 8/9 FT/PipeR [2] I/O0R–I/O7/8R Counter/ Address Register Decode 16/17 [3] A0–A15/16R CLKR ADSR CNTENR CNTRSTR Notes: 1. See page 7 for Load Conditions. 2. I/O0–I/O7 for x8 devices; I/O0–I/O8 for x9 devices. 3. A0–A15 for 64K; and A0–A16 for 128K devices. For the most recent information, visit the Cypress web site at www.cypress.com Cypress Semiconductor Corporation • 3901 North First Street • San Jose • CA 95134 • 408-943-2600 Document #: 38-06039 Rev. A Revised December 27, 2002 DataSheet4 U .com 1 page www.DataSheet4U.com CY7C09089/99 CY7C09189/99 Pin Definitions Left Port A0L–A16L ADSL CE0L,CE1L CLKL CNTENL CNTRSTL I/O0L–I/O8L OEL R/WL FT/PIPEL GND NC VCC Right Port A0R–A16R ADSR CE0R,CE1R CLKR CNTENR CNTRSTR I/O0R–I/O8R OER R/WR FT/PIPER Description Address Inputs (A0−A15 for 64K; and A0−A16 for 128K devices). Address Strobe Input. Used as an address qualifier. This signal should be asserted LOW to access the part using an externally supplied address. Asserting this signal LOW also loads the burst counter with the address present on the address pins. Chip Enable Input. To select either the left or right port, both CE0 AND CE1 must be asserted to their active states (CE0 ≤ VIL and CE1 ≥ VIH). Clock Signal. This input can be free running or strobed. Maximum clock input rate is fMAX. Counter Enable Input. Asserting this signal LOW increments the burst address counter of its respective port on each rising edge of CLK. CNTEN is disabled if ADS or CNTRST are asserted LOW. Counter Reset Input. Asserting this signal LOW resets the burst address counter of its respective port to zero. CNTRST is not disabled by asserting ADS or CNTEN. Data Bus Input/Output (I/O0–I/O7 for x8 devices; I/O0–I/O8 for x9 devices). Output Enable Input. This signal must be asserted LOW to enable the I/O data pins during read operations. Read/Write Enable Input. This signal is asserted LOW to write to the dual port memory array. For read operations, assert this pin HIGH. Flow-Through/Pipelined Select Input. For flow-through mode operation, assert this pin LOW. For pipelined mode operation, assert this pin HIGH. Ground Input. No Connect. Power Input. Maximum Ratings [8] (Above which the useful life may be impaired. For user guide- lines, not tested.) Storage Temperature ................................. –65°C to +150°C Ambient Temperature with Power Applied .. –55°C to +125°C Supply Voltage to Ground Potential ............... –0.3V to +7.0V DC Voltage Applied to Outputs in High Z State ................................. –0.5V to +7.0V DC Input Voltage............................................ –0.5V to +7.0V Output Current into Outputs (LOW)............................. 20 mA Static Discharge Voltage ........................................... >2001V Latch-Up Current...................................................... >200mA Operating Range Range Commercial Industrial[9] Ambient Temperature 0°C to +70°C −40°C to +85°C VCC 5V ± 10% 5V ± 10% Note: 8. The Voltage on any input or I/O pin cannot exceed the power pin during power-up. 9. Industrial parts are available in CY7C09099 and CY7C09199 only. Document #: 38-06039 Rev. A DataSheet4 U .com Page 5 of 19 5 Page www.DataSheet4U.com Switching Waveforms (continued) Pipelined Read-to-Write-to-Read (OE = VIL)[17, 24, 25, 26] tCYC2 tCH2 tCL2 CLK CY7C09089/99 CY7C09189/99 CE0 tSC CE1 R/W tSW tHC tHW tSW tHW ADDRESS DATAIN tSA An tHA DATAOUT An+1 An+2 tCD2 tCKHZ Qn An+2 tSD tHD Dn+2 An+3 tCKLZ An+4 tCD2 Qn+3 READ NO OPERATION Pipelined Read-to-Write-to-Read (OE Controlled)[17, 24, 25, 26] tCYC2 tCH2 tCL2 CLK WRITE READ CE0 tSC tHC CE1 tSW tHW R/W tSW ADDRESS DATAIN tSA An tHW tHA DATAOUT An+1 tCD2 An+2 tSD tHD Dn+2 Qn tOHZ An+3 Dn+3 An+4 An+5 tCKLZ tCD2 Qn+4 OE READ WRITE READ Notes: 24. Output state (HIGH, LOW, or High-Impedance) is determined by the previous cycle control signals. 25. CE0 and ADS = VIL; CE1, CNTEN, and CNTRST = VIH. 26. During “No Operation,” data in memory at the selected address may be corrupted and should be rewritten to ensure data integrity. Document #: 38-06039 Rev. *A Page 11 of 19 DataSheet4 U .com 11 Page

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