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What is M393T5166AZA?

This electronic component, produced by the manufacturer "SAMSUNG", performs the same function as "(M393Txx63AZx) DDR2 Registered SDRAM MODULE".


M393T5166AZA Datasheet PDF - SAMSUNG

Part Number M393T5166AZA
Description (M393Txx63AZx) DDR2 Registered SDRAM MODULE
Manufacturers SAMSUNG　
Logo SAMSUNG Logo　


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1GB, 2GB, 4GB Registered DIMMs
DDR2 SDRAM
DDR2 Registered SDRAM MODULE
240pin Registered Module based on 1Gb A-die
72-bit ECC
INFORMATION IN THIS DOCUMENT IS PROVIDED IN RELATION TO SAMSUNG PRODUCTS,
AND IS SUBJECT TO CHANGE WITHOUT NOTICE.
NOTHING IN THIS DOCUMENT SHALL BE CONSTRUED AS GRANTING ANY LICENSE,
EXPRESS OR IMPLIED, BY ESTOPPEL OR OTHERWISE,
TO ANY INTELLECTUAL PROPERTY RIGHTS IN SAMSUNG PRODUCTS OR TECHNOLOGY. ALL
INFORMATION IN THIS DOCUMENT IS PROVIDED
ON AS "AS IS" BASIS WITHOUT GUARANTEE OR WARRANTY OF ANY KIND.
1. For updates or additional information about Samsung products, contact your nearest Samsung office.
2. Samsung products are not intended for use in life support, critical care, medical, safety equipment, or similar
applications where Product failure couldresult in loss of life or personal or physical harm, or any military or
defense application, or any governmental procurement to which special terms or provisions may apply.
* Samsung Electronics reserves the right to change products or specification without notice.
Rev. 1.2 Sep. 2005
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M393T5166AZA equivalent
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1GB, 2GB, 4GB Registered DIMMs
DDR2 SDRAM
Pin Configurations (Front side/Back side)
Pin Front Pin Back Pin Front Pin Back Pin Front Pin Back Pin Front
1
VREF
121
VSS
31
DQ19
151
VSS
61
A4
181 VDDQ
91
VSS
2
VSS 122 DQ4
32
VSS
152 DQ28
62
VDDQ
182
A3
92 DQS5
3
DQ0 123 DQ5
33 DQ24 153 DQ29 63
A2 183 A1
93 DQS5
4
DQ1 124 VSS
34
DQ25
154
VSS
64
VDD 184 VDD
94
VSS
5
VSS 125 DM0/DQS9 35
VSS 155 DM3/DQS12
KEY
95 DQ42
6
DQS0
126 NC/DQS9 36
DQS3
156 NC/DQS12 65
VSS 185 CK0
96 DQ43
7
DQS0
127
VSS
37
DQS3
157
VSS
66
VSS 186 CK0
97
VSS
8 VSS 128 DQ6 38 VSS 158 DQ30 67 VDD 187 VDD 98 DQ48
9
DQ2 129 DQ7
39 DQ26 159 DQ31 68 NC/Par_In 188
A0
99 DQ49
10
DQ3
130
VSS
40
11
VSS
131 DQ12
41
12
DQ8
132 DQ13
42
13
DQ9
133
VSS
43
14 VSS 134 DM1/DQS10 44
15
DQS1
135 NC/DQS10 45
16
DQS1
136
17 VSS 137
18 RESET 138
VSS
RFU
RFU
46
47
48
19 NC 139 VSS 49
20
VSS
140 DQ14
50
21 DQ10 141 DQ15 51
22
DQ11
142
VSS
52
23
VSS
143 DQ20
53
24 DQ16 144 DQ21 54
DQ27
VSS
CB0
CB1
VSS
DQS8
DQS8
VSS
CB2
CB3
VSS
VDDQ
CKE0
VDD
BA2
160 VSS
161 CB4
162 CB5
163 VSS
164 DM8/DQS17
165 NC/DQS17
166 VSS
167 CB6
168 CB7
169 VSS
170 VDDQ
171 CKE14
172 VDD
173 NC
174 NC
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
VDD
A10/AP
BA0
VDDQ
WE
CAS
VDDQ
S14
ODT1
VDDQ
VSS
DQ32
DQ33
VSS
DQS4
189 VDD 100
190 BA1 101
191 VDDQ 102
192 RAS 103
193 S0 104
194 VDDQ 105
195 ODT0 106
196 A13 107
197 VDD 108
198 VSS 109
199 DQ36 110
200 DQ37 111
201 VSS 112
202 DM4/DQS13 113
203 NC/DQS13 114
VSS
SA2
NC(TEST)
VSS
DQS6
DQS6
VSS
DQ50
DQ51
VSS
DQ56
DQ57
VSS
DQS7
DQS7
25
DQ17
145
VSS
55 NC/Err_Out 175
VDDQ
84
DQS4
204
VSS
115
VSS
26
VSS
146 DM2/DQS11 56
VDDQ
176
A12
85
VSS 205 DQ38 116 DQ58
27
DQS2
147 NC/DQS11 57
A11 177
A9
86 DQ34 206 DQ39 117 DQ59
28
DQS2
148
VSS
58
29
VSS
149 DQ22
59
30 DQ18 150 DQ23 60
A7 178 VDD
VDD
179
A8
A5 180 A6
87
DQ35
207
VSS
118
VSS
88 VSS 208 DQ44 119 SDA
89 DQ40 209 DQ45 120 SCL
90
DQ41
210
VSS
NC = No Connect, RFU = Reserved for Future Use
1. RESET (Pin 18) is connected to both OE of PLL and Reset of register.
2. The Test pin (Pin 102) is reserved for bus analysis probes and is not connected on normal memory modules (DIMMs)
3. NC/Err_Out ( Pin 55) and NC/Par_In (Pin 68) are for optional function to check address and command parity.
4. CKE1,S1 Pin is used for double side Registered DIMM.
Pin Description
Pin Back
211 DM5/DQS14
212 NC/DQS14
213 VSS
214 DQ46
215 DQ47
216 VSS
217 DQ52
218 DQ53
219 VSS
220 RFU
221 RFU
222 VSS
223 DM6/DQS15
224 NC/DQS15
225 VSS
226 DQ54
227 DQ55
228 VSS
229 DQ60
230 DQ61
231 VSS
232 DM7/DQS16
233 NC/DQS16
234 VSS
235 DQ62
236 DQ63
237 VSS
238 VDDSPD
239 SA0
240 SA1
Pin Name
CK0
CK0
CKE0, CKE1
RAS
CAS
WE
S0, S1
A0~A9, A11~A13
A10/AP
Description
Clock Inputs, positive line
Clock inputs, negative line
Clock Enables
Row Address Strobe
Column Address Strobe
Write Enable
Chip Selects
Address Inputs
Address Input/Autoprecharge
BA0~BA2
DDR2 SDRAM Bank Address
SCL Serial Presence Detect (SPD) Clock Input
SDA
SPD Data Input/Output
SA0~SA2
SPD address
Par_In
Parity bit for the Address and Control bus
Err_Out
Parity error found in the Address and Control bus
RESET
Register and PLL control pin
* The VDD and VDDQ pins are tied to the single power-plane on PCB.
Pin Name
Description
ODT0~ODT1
On die termination
DQ0~DQ63
Data Input/Output
CB0~CB7
Data check bits Input/Output
DQS0~DQS8
Data strobes
DQS0~DQS8
Data strobes, negative line
DM(0~8), DQS(9~17) Data Masks / Data strobes (Read)
DQS9~DQS17
Data strobes (Read), negative line
RFU
Reserved for Future Use
NC No Connect
TEST
Memory bus test tool
(Not Connect and Not Useable on DIMMs)
VDD Core Power
VDDQ
I/O Power
VSS Ground
VREF
Input/Output Reference
VDDSPD
SPD Power
Rev. 1.2 Sep. 2005
DataSheet4 U .com


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