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M393T5750BG 데이터시트 PDF




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부품번호 M393T5750BG 기능
기능 (M393Txx5xBG) Registered SDRAM MODULE 240pin Registered Module based
제조업체 SAMSUNG
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M393T5750BG 데이터시트, 핀배열, 회로
www.DataSheet4U.com
512MB, 1GB, 2GB Registered DIMMs
DDR2 SDRAM
DDR2 Registered SDRAM MODULE
240pin Registered Module based on 512Mb B-die
72-bit ECC
INFORMATION IN THIS DOCUMENT IS PROVIDED IN RELATION TO SAMSUNG PRODUCTS,
AND IS SUBJECT TO CHANGE WITHOUT NOTICE.
NOTHING IN THIS DOCUMENT SHALL BE CONSTRUED AS GRANTING ANY LICENSE,
EXPRESS OR IMPLIED, BY ESTOPPEL OR OTHERWISE,
TO ANY INTELLECTUAL PROPERTY RIGHTS IN SAMSUNG PRODUCTS OR TECHNOLOGY. ALL
INFORMATION IN THIS DOCUMENT IS PROVIDED
ON AS "AS IS" BASIS WITHOUT GUARANTEE OR WARRANTY OF ANY KIND.
1. For updates or additional information about Samsung products, contact your nearest Samsung office.
2. Samsung products are not intended for use in life support, critical care, medical, safety equipment, or similar
applications where Product failure couldresult in loss of life or personal or physical harm, or any military or
defense application, or any governmental procurement to which special terms or provisions may apply.
* Samsung Electronics reserves the right to change products or specification without notice.
Rev. 1.3 Aug. 2005
DataSheet4 U .com




M393T5750BG pdf, 반도체, 판매, 대치품
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512MB, 1GB, 2GB Registered DIMMs
DDR2 SDRAM
Input/Output Functional Description
Symbol
CK0
CK0
CKE0~CKE1
S0~S1
ODT0~ODT1
RAS, CAS, WE
VREF
VDDQ
BA0~BA1
A0~A9,A10/AP
A11~A13
DQ0~63,
CB0~CB7
DM0~DM8
VDD, VSS
DQS0~DQS17
DQS0~DQS17
SA0~SA2
SDA
SCL
VDDSPD
RESET
Par_In
Err_Out
TEST
Type
Input
Input
Input
Input
Input
Input
Supply
Function
Positive line of the differential pair of system clock inputs that drives input to the on-DIMM PLL.
Negative line of the differential pair of system clock inputs that drives the input to the on-DIMM PLL.
Activates the SDRAM CK signal when high and deactivates the CK signal when low. By deactivating the clocks, CKE low
initiates the Power Down mode, or the Self Refresh mode.
Enables the associated SDRAM command decoder when low and disables decoder when high. When decoder is dis-
abled, new commands are ignored but previous operations continue.
These input signals also disable all outputs (except CKE and ODT) of the register(s) on the DIMM when both inputs are
high.
I/O bus impedance control signals.
When sampled at the positive rising edge of the clock, CAS, RAS, and WE define the operation to be executed by the
SDRAM.
Reference voltage for SSTL_18 inputs
Supply
Input
Input
Isolated power supply for the DDR SDRAM output buffers to provide improved noise immunity
Selects which SDRAM bank of four is activated.
During a Bank Activate command cycle, Address defines the row address.
During a Read or Write command cycle, Address defines the column address. In addition to the column address, AP is
used to invoke autoprecharge operation at the end of the burst read or write cycle. If AP is high, autoprecharge is
selected and BA0, BA1 defines the bank to be precharged. If AP is low, autoprecharge is disabled. During a Precharge
command cycle, AP is used in conjunction with BA0, BA1 to control which bank(s) to precharge. If AP is high, all banks
will be precharged regardless of the state of BA0 or BA1. If AP is low, BA0 and BA1 are used to define which bank to pre-
charge.
In/Out Data and Check Bit Input/Output pins
Input
Supply
In/Out
In/Out
Input
In/Out
Input
Supply
Input
Input
Input
In/Out
Masks write data when high, issued concurrently with input data. Both DM and DQ have a write latency of one clock once
the write command is registered into the SDRAM.
Power and ground for the DDR SDRAM input buffers and core logic
Positive line of the differential data strobe for input and output data.
Negative line of the differential data strobe for input and output data.
These signals are tied at the system planar to either VSS or VDDSPD to configure the serial SPD EEPROM address range.
This bidirectional pin is used to transfer data into or out of the SPD EEPROM. A resistor must be connected from the SDA
bus line to VDDSPD to act as a pullup.
This signal is used to clock data into and out of the SPD EEPROM. A resistor may be connected from the SCL bus time
to VDDSPD to act as a pullup.
Serial EEPROM positive power supply (wired to a separate power pin at the connector which supports from 1.7 Volt to
3.6 Volt operation).
The RESET pin is connected to the RST pin on the register and to the OE pin on the PLL. When low, all register outputs
will be driven low and the PLL clocks to the DRAMs and register(s) will be set to low level (The PLL will remain synchro-
nized with the input clock )
Parity bit for the Address and Control bus. ( “1 “ : Odd, “0 “ : Even)
Parity error found in the Address and Control bus
Used by memory bus analysis tools (unused on memory DIMMs)
DataSheet4 U .com
Rev. 1.3 Aug. 2005

4페이지










M393T5750BG 전자부품, 판매, 대치품
www.DataSheet4U.com
512MB, 1GB, 2GB Registered DIMMs
DDR2 SDRAM
Functional Block Diagram: 1GB, 128Mx72 Module(populated as 1 rank of x4 DDR2 SDRAMs)
M393T2950BG(Z)3 / M393T2950BG(Z)0
VSS
RS0
DQS0
DQS0
DQ0
DQ1
DQ2
DQ3
DQS1
DQS1
DQ8
DQ9
DQ10
DQ11
DQS2
DQS2
DQ16
DQ17
DQ18
DQ19
DQS3
DQS3
DQ24
DQ25
DQ26
DQ27
DQS4
DQS4
DQ32
DQ33
DQ34
DQ35
DQS5
DQS5
DQ40
DQ41
DQ42
DQ43
DQS6
DQS6
DQ48
DQ49
DQ50
DQ51
DQS7
DQS7
DQ56
DQ57
DQ58
DQ59
DQS8
DQS8
CB0
CB1
CB2
CB3
DM
I/O 0
I/O 1
I/O 2
I/O 3
CS DQS DQS
D0
DM
I/O 0
I/O 1
I/O 2
I/O 3
CS DQS DQS
D1
DM
I/O 0
I/O 1
I/O 2
I/O 3
CS DQS DQS
D2
DM
I/O 0
I/O 1
I/O 2
I/O 3
CS DQS DQS
D3
DM
I/O 0
I/O 1
I/O 2
I/O 3
CS DQS DQS
D4
DM
I/O 0
I/O 1
I/O 2
I/O 3
CS DQS DQS
D5
DM
I/O 0
I/O 1
I/O 2
I/O 3
CS DQS DQS
D6
DM
I/O 0
I/O 1
I/O 2
I/O 3
CS DQS DQS
D7
DM
I/O 0
I/O 1
I/O 2
I/O 3
CS DQS DQS
D8
DM0/DQS9
NC/DQS9
DQ4
DQ5
DQ6
DQ7
DM1/DQS10
NC/DQS10
DQ12
DQ13
DQ14
DQ15
DM2/DQS11
NC/DQS11
DQ20
DQ21
DQ22
DQ23
DM3/DQS12
NC/DQS12
DQ28
DQ29
DQ30
DQ31
DM4/DQS13
NC/DQS13
DQ36
DQ37
DQ38
DQ39
DM5/DQS14
NC/DQS14
DQ44
DQ45
DQ46
DQ47
DM6/DQS15
NC/DQS15
DQ52
DQ53
DQ54
DQ55
DM7DQS16
NC/DQS16
DQ60
DQ61
DQ62
DQ63
DM8/DQS17
NC/DQS17
CB4
CB5
CB6
CB7
DM
I/O 0
I/O 1
I/O 2
I/O 3
CS DQS DQS
D9
DM
I/O 0
I/O 1
I/O 2
I/O 3
CS DQS DQS
D10
DM
I/O 0
I/O 1
I/O 2
I/O 3
CS DQS DQS
D11
DM
I/O 0
I/O 1
I/O 2
I/O 3
CS DQS DQS
D12
DM
I/O 0
I/O 1
I/O 2
I/O 3
CS DQS DQS
D13
DM
I/O 0
I/O 1
I/O 2
I/O 3
CS DQS DQS
D14
DM
I/O 0
I/O 1
I/O 2
I/O 3
CS DQS DQS
D15
DM
I/O 0
I/O 1
I/O 2
I/O 3
CS DQS DQS
D16
DM
I/O 0
I/O 1
I/O 2
I/O 3
CS DQS DQS
D17
SCL
Serial PD
WP A0 A1 A2
SA0 SA1 SA2
SDA
VDDSPD
VDD/VDDQ
VREF
VSS
Serial PD
D0 - D17
D0 - D17
D0 - D17
S0*
BA0-BA1
A0-A13
RAS
CAS
WE
CKE0
ODT0
RESET**
PCK7**
PCK7**
1:2
R
E
G
I
S
T
E
R
RST
CK0
RSO-> CS : DDR2 SDRAMs D0-D17
CK0
RBA0-RBA1 -> BA0-BA1 : DDR2 SDRAMs D0-D17
RA0-RA13 -> A0-A13 : DDR2 SDRAMs D0-D17 RESET
RRAS -> RAS : DDR2 SDRAMs D0-D17
RCAS -> CAS : DDR2 SDRAMs D0-D17
RWE -> WE : DDR2 SDRAMs D0-D17
RCKE0 -> CKE : DDR2 SDRAMs D0-D17
RODT0 -> ODT0 : DDR2 SDRAMs D0-D17
PCK0-PCK6, PCK8, PCK9 -> CK : DDR2 SDRAMs D0-D8
P
L
L PCK0-PCK6, PCK8, PCK9 -> CK : DDR2 SDRAMs D0-D8
OE
PCK7 -> CK : Register
PCK7 -> CK : Register
Notes :
1. DQ-to-I/O wiring may be changed per nibble.
2. Unless otherwise noted, resister values are 22 Ohms
* S0 connects to DCS of Register1, CSR of Register2. CSR of register 1 and DCS of register 2 connects to VDD
** RESET, PCK7 and PCK7 connects to both Registers. Other signals connect to one of two Registers.
DataSheet4 U .com
Rev. 1.3 Aug. 2005

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M393T5750BG

(M393Txx5xBG) Registered SDRAM MODULE 240pin Registered Module based

SAMSUNG
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