PDF ADF4002 Data sheet ( Hoja de datos )

Número de pieza	ADF4002
Descripción	Phase Detector/Frequency Synthesizer
Fabricantes	Analog Devices
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No Preview Available ! Data Sheet Phase Detector/Frequency Synthesizer ADF4002 FEATURES 400 MHz bandwidth 2.7 V to 3.3 V power supply Separate charge pump supply (VP) allows extended tuning voltage in 3 V systems Programmable charge pump currents 3-wire serial interface Analog and digital lock detect Hardware and software power-down mode 104 MHz phase detector APPLICATIONS Clock conditioning Clock generation IF LO generation GENERAL DESCRIPTION The ADF4002 frequency synthesizer is used to implement local oscillators in the upconversion and downconversion sections of wireless receivers and transmitters. It consists of a low noise digital phase frequency detector (PFD), a precision charge pump, a programmable reference divider, and programmable N divider. The 14-bit reference counter (R counter) allows selectable REFIN frequencies at the PFD input. A complete phase-locked loop (PLL) can be implemented if the synthesizer is used with an external loop filter and voltage controlled oscillator (VCO). In addition, by programming R and N to 1, the device can be used as a standalone PFD and charge pump. REFIN CLK DATA LE RFINA RFINB AVDD DVDD 24-BIT INPUT REGISTER 22 SDOUT FUNCTIONAL BLOCK DIAGRAM VP CPGND REFERENCE RSET 14-BIT R COUNTER 14 R COUNTER LATCH FUNCTION LATCH N COUNTER LATCH PHASE FREQUENCY DETECTOR CHARGE PUMP CP LOCK DETECT CURRENT SETTING 1 CURRENT SETTING 2 CPI3 CPI2 CPI1 CPI6 CPI5 CPI4 AVDD SDOUT MUX HIGH Z MUXOUT 13-BIT N COUNTER M3 M2 M1 ADF4002 CE AGND DGND Figure 1. Rev. D Document Feedback Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibilityisassumedbyAnalogDevices for itsuse,nor foranyinfringementsofpatentsor other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarksandregisteredtrademarksarethepropertyoftheirrespectiveowners. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781.329.4700 ©2006–2015 Analog Devices, Inc. All rights reserved. Technical Support www.analog.com 1 page ADF4002 Data Sheet Parameter NOISE CHARACTERISTICS Normalized Phase Noise Floor (PNSYNTH)6 Normalized 1/f Noise (PN1_f)7 B Version1 Min Typ Max −222 −119 Unit Test Conditions/Comments dBc/Hz PLL loop bandwidth = 500 kHz, measured at 100 kHz offset dBc/Hz 10 kHz offset; normalized to 1 GHz 1 Operating temperature range (B version) is −40°C to +85°C. 2 AVDD = DVDD = 3 V. 3 AC coupling ensures AVDD/2 bias. 4 Guaranteed by design. Sample tested to ensure compliance. 5 TA = 25°C; AVDD = DVDD = 3 V; RFIN = 350 MHz. The current for any other setup (25°C, 3.0 V) in mA is given by 2.35 + 0.0046 (REFIN) + 0.0062 (RF), RF frequency and REFIN frequency in MHz. 6 The synthesizer phase noise floor is estimated by measuring the in-band phase noise at the output of the VCO and subtracting 20 logN (where N is the N divider value) and 10 logFPFD. PNSYNTH = PNTOT – 10 logFPFD – 20 logN. 7 The PLL phase noise is composed of 1/f (flicker) noise plus the normalized PLL noise floor. The formula for calculating the 1/f noise contribution at an RF frequency, fRF, and at a frequency offset, f, is given by PN = PN1_f + 10 log(10 kHz/f) + 20 log(fRF/1 GHz). All phase noise measurements were performed with the EV-ADF4002SD1Z and the Agilent E5500 phase noise system. Both the normalized phase noise floor and flicker noise are modeled in ADIsimPLL. TIMING CHARACTERISTICS AVDD = DVDD = 3 V ± 10%, AVDD ≤ VP ≤ 5.5 V, AGND = DGND = CPGND = 0 V, RSET = 5.1 kΩ, dBm referred to 50 Ω, TA = TMAX to TMIN, unless otherwise noted.1 Table 2. Parameter t1 t2 t3 t4 t5 t6 Limit (B Version)2 10 10 25 25 10 20 Unit ns min ns min ns min ns min ns min ns min Test Conditions/Comments DATA to CLK setup time DATA to CLK hold time CLK high duration CLK low duration CLK to LE setup time LE pulse width 1 Guaranteed by design, but not production tested. 2 Operating temperature range (B version) is −40°C to +85°C. Timing Diagram t3 t4 CLK DATA DB23 (MSB) t1 t2 DB22 LE LE DB2 DB1 (CONTROL BIT C2) DB0 (LSB) (CONTROL BIT C1) t6 t5 Figure 2. Timing Diagram Rev. D \| Page 4 of 20 5 Page ADF4002 Data Sheet LATCH MAPS AND DESCRIPTIONS LATCH SUMMARY REFERENCE COUNTER LATCH RESERVED TEST MODE BITS ANTI- BACKLASH WIDTH 14-BIT REFERENCE COUNTER CONTROL BITS DB23 DB22 DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 X 0 0 LDP T2 T1 ABP2 ABP1 R14 R13 R12 R11 R10 R9 R8 R7 R6 R5 R4 R3 R2 R1 C2 (0) C1 (0) N COUNTER LATCH RESERVED 13-BIT N COUNTER RESERVED CONTROL BITS DB23 DB22 DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 X X G1 B13 B12 B11 B10 B9 B8 B7 B6 B5 B4 B3 B2 B1 X X X X X X C2 (0) C1 (1) FUNCTION LATCH RESERVED CURRENT SETTING 2 CURRENT SETTING 1 TIMER COUNTER CONTROL MUXOUT CONTROL CONTROL BITS DB23 DB22 DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 X X PD2 CPI6 CPI5 CPI4 CPI3 CPI2 CPI1 TC4 TC3 TC2 TC1 F5 F4 F3 F2 M3 M2 M1 PD1 F1 C2 (1) C1 (0) INITIALIZATION LATCH RESERVED CURRENT SETTING 2 CURRENT SETTING 1 TIMER COUNTER CONTROL MUXOUT CONTROL CONTROL BITS DB23 DB22 DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 X X PD2 CPI6 CPI5 CPI4 CPI3 CPI2 CPI1 TC4 TC3 TC2 TC1 F5 F4 F3 F2 M3 M2 M1 PD1 F1 C2 (1) C1 (1) Figure 15. Latch Summary Rev. D \| Page 10 of 20 11 Page

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