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PDF NCP1378 Data sheet ( Hoja de datos )
| Número de pieza | NCP1378 | |
| Descripción | PWM Current-Mode Controller | |
| Fabricantes | ON Semiconductor | |
| Logotipo |  |
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NCP1378
PWM Current−Mode
Controller for Free−Running
Quasi−Resonant Operation
The NCP1378 combines a true current mode modulator and
a demagnetization detector to ensure full borderline/critical
Conduction Mode in any load/line conditions and minimum drain
voltage switching (Quasi−Resonant operation). Due to its inherent
skip cycle capability, the controller enters burst mode as soon as the
power demand falls below a predetermined level. As this happens at
low peak current, no audible noise can be heard. An internal 8.0 ms
timer prevents the free−run frequency to exceed 100 kHz (therefore
below the 150 kHz CISPR−22 EMI starting limit), while the skip
adjustment capability lets the user select the frequency at which the
burst foldback takes place.
The transformer core reset detection is done through an auxiliary
winding which, brought via a dedicated pin, also enables fast Over
Voltage Protection (OVP). Once an OVP has been detected, the IC
permanently latches off.
The NCP1378 also features an efficient protective circuitry that, in
presence of an overcurrent condition, disables the output pulses and
enters a safe burst mode, trying to restart. Once the default has gone,
the device auto−recovers. Finally an internal 1.0 ms Soft−Start
eliminates the traditional startup stress.
The NCP1378 is tailored for low voltage applications having
UVLO thresholds of 8.4 V (on) and 7.5 V (off).
Features
• Pb−Free Package is Available*
• Free−Running Borderline/Critical Mode Quasi−Resonant Operation
• Latched Overvoltage Protection
• Auto−Recovery Short−Circuit Protection Via UVLO Crossover
• Current−Mode with Adjustable Skip Cycle Capability
• Internal 1.0 ms Soft−Start
• Internal Temperature Shutdown
• Internal Leading Edge Blanking
• 500 mA Peak Current Source/Sink Capability
• External Latch Triggering, e.g. Via Overtemperature Signal
• Direct Optocoupler Connection
• SPICE Models Available for TRANsient Analysis
• Internal 8.0 ms Minimum TOFF
Typical Applications
• Battery−Based Operations
*For additional information on our Pb−Free strategy and soldering details, please
download the ON Semiconductor Soldering and Mounting Techniques Reference
Manual, SOLDERRM/D.
http://onsemi.com
MARKING
DIAGRAMS
8
1
SOIC−8
D SUFFIX
CASE 751
8
1378
ALYW
1
8
1
PDIP−7
P SUFFIX
CASE 626B
1
1378P
AWL
YYWW
A = Assembly Location
WL, L = Wafer Lot
YY, Y = Year
WW, W = Work Week
PIN CONNECTIONS
Dmg 1
FB 2
CS 3
GND 4
8 HV
6 VCC
5 Drv
(Top View)
ORDERING INFORMATION
Device
Package
Shipping†
NCP1378DR2
SOIC−8 2500 Tape & Reel
NCP1378P
PDIP−7
50 Units/Tube
NCP1378PG
PDIP−7
(Pb−Free)
50 Units/Tube
†For information on tape and reel specifications,
including part orientation and tape sizes, please
refer to our Tape and Reel Packaging Specifications
Brochure, BRD8011/D.
© Semiconductor Components Industries, LLC, 2004
October, 2004 − Rev. 1
DataSheet4 U .com
1
Publication Order Number:
NCP1378/D
1 page  
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NCP1378
TYPICAL CHARACTERISTICS
8.8 8.0
8.6 7.8
8.4 7.6
8.2 7.4
8.0 7.2
7.8
−25
0
25 50 75 100 125
TEMPERATURE (°C)
Figure 3. VCCON Threshold versus Temperature
7.0
−25
0
25 50 75 100 125
TEMPERATURE (°C)
Figure 4. VCCMIN Threshold versus Temperature
1.6 2.2
1.4 2.0
1.2 1.8
1.0 1.6
0.8 1.4
0.6 1.2
0.4
−25
0
25 50 75 100 125
TEMPERATURE (°C)
Figure 5. Current Consumption (No Load)
versus Temperature
8
7
6
5
4
3
2
1
0
−25 0
25 50 75 100 125
TEMPERATURE (°C)
Figure 7. HV Current Source at VCC = 10 V
versus temperature
1.0
−25
0
25 50 75
TEMPERATURE (°C)
100 125
Figure 6. Current Consumption (1.0 nF Load)
versus Temperature
1.10
1.05
1.00
0.95
0.90
−25
0
25 50 75 100 125
TEMPERATURE (°C)
Figure 8. Maximum Current Setpoint versus
Temperature
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CTN
NCP1378
NCP1378
18
27
36
45
Aux.
ON/OFF
NCP1378
18
27
36
45
Aux.
VCCcap
Figure 24. A simple CTN triggers the latchoff as
soon as the temperature exceeds a given setpoint.
Figure 25. A simple transistor arrangement allows
to trigger the latchoff by an external signal.
Shutting Off the NCP1378
Shutdown can easily be implemented through a simple
NPN bipolar transistor as depicted by Figure 6. When OFF,
Q1 is transparent to the operation. When forward biased,
the transistor pulls the FB pin to ground (Vcesat [
200 mV) and permanently disables the IC. A small time
constant on the transistor base will avoid false triggering
(Figure 26).
10 k
ON/OFF
3
2
10 nF
NCP1378
18
2
1
3
Q1
4
7
6
5
Figure 26. A Simple Bipolar Transistor Totally
Disables the IC
Overload Operation
In applications where the output current is purposely not
controlled (e.g. wall adapters delivering raw DC level), it
is interesting to implement a true short−circuit protection.
A short−circuit actually forces the output voltage to be at
a low level, preventing a bias current to circulate in the
optocoupler LED. As a result, the auxiliary voltage also
decreases because it also operates in Flyback and thus
duplicates the output voltage, providing the leakage
inductance between windings is kept low. To account for
this situation and properly protect the power supply,
NCP1378 hosts a dedicated overload detection circuitry.
Once activated, this circuitry imposes to deliver pulses in
a burst manner with a low Duty Cycle. The system
auto−recovers when the fault condition disappears.
During the startup phase, the peak current is pushed to
the maximum until the output voltage reaches its target and
the feedback loop takes over. The auxiliary voltage takes
place after a few switching cycles and self−supplies the IC.
In presence of a short circuit on the output, the auxiliary
voltage will go down until it crosses the undervoltage
lockout level of typically 7.5 V. When this happens,
NCP1378 immediately stops the switching pulses and
unbiases all unnecessary logical blocks. The overall
consumption drops, while keeping the gate grounded, and
the VCC slowly falls down. As soon as VCC reaches
typically 5.5 V, the startup source turns−on again and a new
startup sequence occurs, bringing VCC toward 8.4 V as an
attempt to restart. If the default has gone, then the power
supply normally restarts. If not, a new protective burst is
initiated, shielding the SMPS from any runaway.
Figure 27 portrays the typical operating signals in short
circuit.
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