|
|
PDF ADC82124 Data sheet ( Hoja de datos )
| Número de pieza | ADC82124 | |
| Descripción | 24 Ports 10/100 Fast Ethernet Switch Controller | |
| Fabricantes | ETC | |
| Logotipo |  |
|
Hay una vista previa y un enlace de descarga de ADC82124 (archivo pdf) en la parte inferior de esta página. Total 48 Páginas | ||
|
No Preview Available !
www.DataSheet4U.com
Advanced
Communication
Devices
Data Sheet: ACD82124
24 Ports 10/100 Fast Ethernet Switch Controller
Rev.1.1.1.F
Last Update: November 5, 1998
Subject to Change
Please check ACD’s website for
update information before starting a design
Web site: http://www.acdcorp.com
or Contact ACD at:
Email: [email protected]
Tel: 408-433-9898x115
Fax: 408-545-0930
ACD Confidential Material
For ACD authorized customer use only. No reproduction or redistribution without ACD’s prior permission.
DataSheet4 U .com
1
1 page  
www.DataSheet4U.com
5. FUNCTIONAL DESCRIPTION
The MAC controller performs transmit, receive, and
defer functions, in accordance to IEEE 802.3 and
802.3u standard specification. The MAC logic also
handles frame detection, frame generation, error de-
tection, error handling, status indication and flow con-
trol functions.
Frame Format
The ACD82124 assumes that the received data packet
will have the following format:
Preamble SFD DA SA Type/Len Data FCS
Where,
• Preamble is a repetitive pattern of ‘1010….’ of
any length with nibble alignment.
• SFD (Start Frame Delimiter) is defined as an oc-
tet pattern of 10101011.
• DA (Destination Address) is a 48-bit field that speci-
fies the MAC address of the destined DTE. If the
first bit of DA is 1, the ACD82124 will treat the
frame as a broadcast/multicast frame and will for-
ward the frame to all ports within the source port’s
VLAN except the source port itself or BPDU ad-
dress.
• SA (Source Address) is a 48-bit field that con-
tains the MAC address of the source DTE that is
transmitting the frame to the ACD82124. After a
frame is received with no error, the SA is learned
as the port’s MAC address.
• Type/Len field is a 2-byte field that specifies the
type (DIX Ethernet frame) or length (IEEE 802.3
frame) of the frame. The ACD82124 does not pro-
cess this information.
• Data is the encapsulated information within the
Ethernet Packet. The ACD82124 does not pro-
cess any of the data information in this field.
• FCS (Frame Check Sequence) is a 32-bit field of
a CRC (Cyclic Redundancy Check) value based
on the destination address, the source address,
the type/length and the data field. The ACD82124
will verify the FCS field for each frame. The pro-
cedure of computing FCS is described in section
of “FCS Calculation.”
Start of Frame Detection
When a port’s MAC is idle, assertion of the RXDV in
the MII interface will cause the port to go into the re-
ceive state. The MII presents the received data in 4-bit
nibbles that are synchronous to the receive clock
(25Mhz or 2.5MHz). The ACD82124 will convert this
data into a serial bit stream, and attempt to detect the
occurrence of the SFD (10101011) pattern. All data
prior to the detection of SFD are discarded. Once SFD
is detected, the following frame data are forwarded
and stored in the buffer of the switch.
Frame Reception
Under normal operating conditions, the ACD82124
expects a received frame to have a minimum inter frame
gap (IFG). The minimum IFG required by the device is
80 BT (Bit Time).
In the event the ACD82124 receives a packet with IFG
less than 80BT, the ACD82124 does not guarantee to
be able to receive the frame. The packet will be dropped
if the ACD82124 cannot receive the frame.
The device will check all received frames for errors
such as symbol error, FCS error, short event, runt,
long event, jabber etc. Frames with any kind of error
will not be forwarded to any port.
Preamble Bit Processing
The preamble bit in the header of each frame will be
used to synchronize the MAC logic with the incoming
bit stream. The minimum length of the preamble is 0
bits and there is no limitation on the maximum length of
preamble. After the receive data valid signal RXDV is
asserted by the external PHY device, the port will wait
for the occurrence of the SFD pattern (10101011) and
then start a frame receiving process.
Source Address and Destination Address
After a frame is received by the ACD82124, the em-
bedded destination address and source address are
retrieved. The destination address is passed to the
lookup table to find the destination port. The source
address is automatically stored into the address lookup
table. For applications that use an external ARL, the
ACD82124 will disable the internal lookup table and
pass the DA and SA to the external ARL for address
lookup and learning.
DataSheet4 U .com
5
5 Page 
www.DataSheet4U.com
6. INTERFACE DESCRIPTION
MII Interface (MII)
The ACD82124 communicates with the external 10/
100 Ethernet transceivers through standard MII inter-
face. The signals of MII interface are described in
table-6.1:
Table-6.1: MII Interface Signals
Name
Type
Description
PxCRS
I Carrier sense
PxRXDV
I Receive data valid
PxRXCLK I Receive clock (25/2.5 MHz)
PxRXERR I
Receive error
PxRXD0
I Receive data bit 0
PxRXD1
I Receive data bit 1
PxRXD2
I Receive data bit 2
PxRXD3
I Receive data bit 3
PxCOL
I Collision indication
PxTXEN
O Transmit data valid
PxTXCLK I Transmit clock (25/2.5 MHz)
PxTXD0
O Transmit data bit 0
PxTXD1
O Transmit data bit 1
PxTXD2
O Transmit data bit 2
PxTXD3
O Transmit data bit 3
Table-6.2: Reversed MII Interface Signals
Name Type
Description
PxCRSR
O Carrier sense
PxRXDVR I Transmit data valid
PxRXCLKR O Transmit clock (25/2.5 MHz)
PxRXERR I
Not-Ready (Input)
PxRXD0R I Transmit data bit 0
PxRXD1R I Transmit data bit 1
PxRXD2R I Transmit data bit 2
PxRXD3R I Transmit data bit 3
PxCOLR
O
Collision Indication/
Not-Ready (Output)
PxTXENR O Receive data valid
PxTXCLKR O Receive clock (25/2.5 MHz)
PxTXD0R O Receive data bit 0
PxTXD1R O Receive data bit 1
PxTXD2R O Receive data bit 2
PxTXD3R O Receive data bit 3
For reversed MII interface, signal PxRXDVR, and
PxRXD0R through PxRXD3R are clocked out by the
falling edge of PxRXCLKR. Signal PxTXENR, and
PxTXD0R through PxTXD3R can be sampled by the
falling edge or rising edge of PxTXCLKR, depends on
the setting of bit 9 of Register 16. The timing behavior
is described in the chapter of “Timing Description.“
For MII interface, signal PxRXDV, PxRXER and
PxRXD0 through PxRXD3 are sampled by the rising
edge of PxRXCLK. Signal PxTXEN, and PxTXD0
through PxTXD3 are clocked out by the falling edge of
PxTXCLK. The detailed timing requirement is described
in the chapter of “Timing Description”
Ports 0,1, 2, 3, 4, 5, 6, 7, 22 and 23 can be config-
ured as reversed MII ports (Register 28, the Reversed
MII Enable register). These ports, when configured as
“normal” MII, have the same characteristics as all other
MII ports. However, when configured as reversed MII
interface, they will behave logically like a PHY device,
and can interface directly with a MAC device. The
signal of reversed MII interface are described by table-
6.2:
Note: * Collision Indication for half-duplex mode.
Not-Ready (output) for full duplex mode.
PHY Management Interface
All control and status registers of the PHY devices are
accessible through the PHY management interface.
The interface consists of two signals: MDC and MDIO,
which are described in Table-6.3.
Table-6.3: PHY Management Interface Signals
Name Type
Description
MDC O PHY management clock (1.25MHz)
MDIO I/O PHY management data
Frames transmitted on MDIO has the following format
(Table-6.4):
Table-6.4: MDIO Format
Operation
PRE
Write
1…1
Read
1…1
ST
01
01
DataSheet4 U .com
OP PHY-ID REG-AD TA
01
aaaaa
rrrrr
10
10
aaaaa
rrrrr
Z0
DATA
d…d
d…d
IDLE
Z
Z
11
11 Page | ||
| Páginas | Total 48 Páginas | |
| PDF Descargar | [ Datasheet ADC82124.PDF ] | |
Hoja de datos destacado
| Número de pieza | Descripción | Fabricantes |
| ADC82124 | 24 Ports 10/100 Fast Ethernet Switch Controller | ETC |
| Número de pieza | Descripción | Fabricantes |
| SLA6805M | High Voltage 3 phase Motor Driver IC. |
 Sanken |
| SDC1742 | 12- and 14-Bit Hybrid Synchro / Resolver-to-Digital Converters. |
 Analog Devices |
|
DataSheet.es es una pagina web que funciona como un repositorio de manuales o hoja de datos de muchos de los productos más populares, |
| DataSheet.es | 2020 | Privacy Policy | Contacto | Buscar |