Datasheet.kr   

ATR0621 데이터시트 PDF




ATMEL Corporation에서 제조한 전자 부품 ATR0621은 전자 산업 및 응용 분야에서
광범위하게 사용되는 반도체 소자입니다.


 

PDF 형식의 ATR0621 자료 제공

부품번호 ATR0621 기능
기능 GPS Baseband Processor
제조업체 ATMEL Corporation
로고 ATMEL Corporation 로고


ATR0621 데이터시트 를 다운로드하여 반도체의 전기적 특성과 매개변수에 대해 알아보세요.




전체 20 페이지수

미리보기를 사용할 수 없습니다

ATR0621 데이터시트, 핀배열, 회로
www.DataSheet4U.com
Features
16 Channel GPS Correlator
– 8192 Search Bins with GPS Acquisition Accelerator
– Accuracy: 2.5m CEP (Stand-Alone, S/A off)
– Time to First Fix: 34s (Cold Start)
– Acquisition Sensitivity: –140 dBm
– Tracking Sensitivity: –150 dBm
Utilizes the ARM7TDMI® ARM® Thumb® Processor Core
– High-performance 32-bit RISC Architecture
– High-density 16-bit Instruction Set
– Embedded ICE (In-circuit Emulator)
128 Kbyte Internal RAM
384 Kbyte Internal ROM with u-blox GPS Firmware
Fully Programmable External Bus Interface (EBI)
– Maximum External Address Space of 8 Mbytes
– Up to 4 Chip Selects
– Software Programmable 8-bit/16-bit External Data Bus
6-channel Peripheral Data Controller (PDC)
8-level Priority, Individually Maskable, Vectored Interrupt Controller
– 2 External Interrupts
32 User-programmable I/O Lines
1 USB Device Port
– Universal Serial Bus (USB) V2.0 Full-speed Device Specification Compliant
– Embedded USB V2.0 Full-speed Transceiver
– Suspend/Resume Logic
– Ping-pong Mode for Isochronous and Bulk Endpoints
2 USARTs
– 2 Dedicated Peripheral Data Controller (PDC) Channels per USART
Master/Slave SPI Interface
– 2 Dedicated Peripheral Data Controller (PDC) Channels
– 8-bit to 16-bit Programmable Data Length
– 4 External Slave Chip Selects
Programmable Watchdog Timer
Advanced Power Management Controller (APMC)
– Peripherals Can Be Deactivated Individually
– Geared Master Clock to Reduce Power Consumption
– Sleep State with Disabled Master Clock
– Hibernate State with 32.768 kHz Master Clock
Real Time Clock (RTC)
2.3V to 3.6V or 1.8V Supply Voltage
Includes Power Supervisor
1.8V to 3.3V User-definable I/O Voltage for Several GPIOs with 5V Tolerance
1 Kbyte Battery Backup Memory
9 mm × 9 mm 100-pin BGA Package (LFBGA100)
GPS Baseband
Processor
ATR0621
Summary
Preliminary
Electrostatic sensitive device.
Observe precautions for handling.
DataSheet4 U .com
Rev. 4890AS–GPS–09/05
Note: This is a summary document. A complete document
is available under NDA. For more information, please con-
tact your local Atmel sales office.




ATR0621 pdf, 반도체, 판매, 대치품
www.DataSheet4U.com
2. Architectural Overview
2.1 Description
The ATR0621 architecture consists of two main buses, the Advanced System Bus (ASB) and
the Advanced Peripheral Bus (APB). The ASB is designed for maximum performance. It inter-
faces the processor with the on-chip 32-bit memories and the external memories and devices
by means of the External Bus Interface (EBI). The APB is designed for accesses to on-chip
peripherals and is optimized for low power consumption. The AMBA Bridge provides an inter-
face between the ASB and the APB.
An on-chip Peripheral Data Controller (PDC2) transfers data between the on-chip
USARTs/SPI and the on-chip and off-chip memories without processor intervention. Most
importantly, the PDC2 removes the processor interrupt handling overhead and significantly
reduces the number of clock cycles required for a data transfer. It can transfer up to 64K con-
tiguous bytes without reprogramming the starting address. As a result, the performance of the
microcontroller is increased and the power consumption reduced.
The ATR0621 peripherals are designed to be easily programmable with a minimum number of
instructions. Each peripheral has a 16 Kbyte address space allocated in the upper 3 Mbyte of
the 4 Gbyte address space. (Except for the interrupt controller, which has 4 Kbyte address
space.) The peripheral base address is the lowest address of its memory space. The periph-
eral register set is composed of control, mode, data, status, and interrupt registers.
To maximize the efficiency of bit manipulation, frequently written registers are mapped into
three memory locations. The first address is used to set the individual register bits, the second
resets the bits, and the third address reads the value stored in the register. A bit can be set or
reset by writing a “1” to the corresponding position at the appropriate address. Writing a “0”
has no effect. Individual bits can thus be modified without having to use costly read-modify-
write and complex bit-manipulation instructions.
All of the external signals of the on-chip peripherals are under the control of the Parallel I/O
(PIO2) Controller. The PIO2 Controller can be programmed to insert an input filter on each pin
or generate an interrupt on a signal change. After reset, the user must carefully program the
PIO2 Controller in order to define which peripheral signals are connected with off-chip logic.
The ARM7TDMI® processor operates in little-endian mode on the ATR0621 GPS Baseband.
The processor's internal architecture and the ARM® and Thumb® instruction sets are
described in the ARM7TDMI datasheet. The memory map and the on-chip peripherals are
described in detail in the ATR0621 full datasheet. The electrical and mechanical characteris-
tics are also documented in the ATR0621 full datasheet.
The ARM standard In-Circuit Emulation debug interface is supported via the JTAG/ICE port of
the ATR0621.
Features of the ROM firmware are described in software documentation available from u-blox
AG.
4 ATR0621 [Preliminary]
DataSheet4 U .com
4890AS–GPS–09/05

4페이지










ATR0621 전자부품, 판매, 대치품
www.DataSheet4U.com
ATR0621 [Preliminary]
Table 3-1. ATR0621 Pinout (Continued)
Pin Name LFBGA100 Pin Type
Pull Resistor
(Reset Value)(1) Firmware Label
PIO Bank A
PIO Bank B
P6 A8
I/O
OH NOE/NRD
NOE/NRD
“0”
P7 D2
I/O
OH NUB/NWR1
NUB/NWR1
“0”
P8 G2
I/O
STATUSLED
“0”
P9 J8
I/O
PU
EXTINT0
EXTINT0
P10 E4
I/O
OH EM_A0/NLB
EM_A0/NLB
“0”
P11 H10
I/O
OH EM_A21
NCS2
EM_A21
P12 F3
I/O Configurable (PU) GPSMODE2
NPCS2
P13 G10
I/O
PU GPSMODE3 EXTINT1
P14 J5
I/O Configurable (PD) NAADET1
“0”
P15 K5
I/O
PD ANTON
P16 E1
I/O
Configurable (PU) NEEPROM
SIGHI1
NWD_OVF
P17 J4
I/O
Configurable (PD) GPSMODE5
SCK1
SCK1
P18 K4
I/O Configurable (PU) TXD1
TXD1
“0”
P19 F1
I/O Configurable (PU) GPSMODE6 SIGLO1
“0”
P20 H2
I/O
Configurable (PU) TIMEPULSE
SCK2
SCK2
TIMEPULSE
P21 F2
I/O Configurable (PU) TXD2
TXD2
“0”
P22 H8
I/O
PU
RXD2
RXD2
P23 H3
I/O Configurable (PU) GPSMODE7 SCK
SCK
MCLK_OUT
P24 H1
I/O
Configurable (PU) GPSMODE8
MOSI
MOSI
“0”
P25 D1
I/O Configurable (PU) NAADET0
MISO
MISO
“0”
P26 G8
I/O
Configurable (PU) GPSMODE10
NSS
NPCS0
“0”
P27 E2
I/O Configurable (PU) GPSMODE11
NPCS1
P28 G1
I/O
OH EM_A20
NCS3
EM_A20
P29 E3
I/O Configurable (PU) GPSMODE12
NPCS3
P30 G5
I/O
PD AGCOUT0
AGCOUT0
“0”
P31 H9
I/O
PU
RXD1
RXD1
RF_ON
K6
OUT
PD
SIGHI0
F9
OUT
SIGLO0
E10
OUT
TCK
J3
IN
PU
TDI J2
IN
PU
TDO
K3
OUT
TMS
J1
IN
PU
USB_DM
F10
I/O
USB_DP
D3
I/O
VBAT
J7
IN
Notes: 1. PD = internal pull-down resistor, PU = internal pull-up resistor, OH = switched to Output High at reset
2. VDDIO is the supply voltage for the following GPIO pins: P1, P2, P8, P12, P14, P16, P17, P18, P19, P20, P21, P23, P24,
P25, P26, P27 and P29
3. VDD_USB is the supply voltage for the following USB pins: USB_DM and USB_DP. For operation of the USB interface, sup-
ply of 3.0V to 3.6V is required.
4890AS–GPS–09/05
DataSheet4 U .com
7

7페이지


구       성 총 20 페이지수
다운로드[ ATR0621.PDF 데이터시트 ]

당사 플랫폼은 키워드, 제품 이름 또는 부품 번호를 사용하여 검색할 수 있는

포괄적인 데이터시트를 제공합니다.


구매 문의
일반 IC 문의 : 샘플 및 소량 구매
-----------------------------------------------------------------------

IGBT, TR 모듈, SCR 및 다이오드 모듈을 포함한
광범위한 전력 반도체를 판매합니다.

전력 반도체 전문업체

상호 : 아이지 인터내셔날

사이트 방문 :     [ 홈페이지 ]     [ 블로그 1 ]     [ 블로그 2 ]



관련 데이터시트

부품번호상세설명 및 기능제조사
ATR0620

GPS BASEBAND PROCESSOR

ATMEL Corporation
ATMEL Corporation
ATR0621

GPS Baseband Processor

ATMEL Corporation
ATMEL Corporation

DataSheet.kr       |      2020   |     연락처      |     링크모음      |      검색     |      사이트맵