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부품번호 | AD9222 기능 |
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기능 | 40/50 MSPS Serial LVDS 1.8 V A/D Converter | ||
제조업체 | Analog Devices | ||
로고 | |||
전체 30 페이지수
Data Sheet
FEATURES
8 ADCs integrated into 1 package
114 mW ADC power per channel at 65 MSPS
SNR = 70 dB (to Nyquist)
ENOB = 11.3 bits
SFDR = 80 dBc
Excellent linearity: DNL = ±0.3 LSB (typical),
INL = ±0.4 LSB (typical)
Serial LVDS (ANSI-644, default)
Low power, reduced signal option (similar IEEE 1596.3)
Data and frame clock outputs
325 MHz full-power analog bandwidth
2 V p-p input voltage range
1.8 V supply operation
Serial port control
Full-chip and individual-channel power-down modes
Flexible bit orientation
Built-in and custom digital test pattern generation
Programmable clock and data alignment
Programmable output resolution
Standby mode
APPLICATIONS
Medical imaging and nondestructive ultrasound
Portable ultrasound and digital beam-forming systems
Quadrature radio receivers
Diversity radio receivers
Tape drives
Optical networking
Test equipment
GENERAL DESCRIPTION
The AD9222 is an octal, 12-bit, 40/50/65 MSPS analog-to-
digital converter (ADC) with an on-chip sample-and-hold
circuit designed for low cost, low power, small size, and ease of
use. The product operates at a conversion rate of up to 65 MSPS
and is optimized for outstanding dynamic performance and low
power in applications where a small package size is critical.
The ADC requires a single 1.8 V power supply and LVPECL-/
CMOS-/LVDS-compatible sample rate clock for full performance
operation. No external reference or driver components are
required for many applications.
The ADC automatically multiplies the sample rate clock for
the appropriate LVDS serial data rate. A data clock output (DCO)
for capturing data on the output and a frame clock output (FCO)
for signaling a new output byte are provided. Individual-channel
power-down is supported and typically consumes less than
2 mW when all channels are disabled.
Octal, 12-Bit, 40/50/65 MSPS
Serial LVDS 1.8 V A/D Converter
AD9222
FUNCTIONAL BLOCK DIAGRAM
AVDD
PDWN
DRVDD DRGND
VIN + A
VIN – A
VIN + B
VIN – B
VIN + C
VIN – C
VIN + D
VIN – D
VIN + E
VIN – E
VIN + F
VIN – F
VIN + G
VIN – G
VIN + H
VIN – H
VREF
SENSE
REFT
REFB
AD9222
ADC
ADC
ADC
ADC
ADC
ADC
ADC
ADC
REF
SELECT
0.5V
SERIAL PORT
INTERFACE
12
SERIAL
LVDS
12
SERIAL
LVDS
12
SERIAL
LVDS
12
SERIAL
LVDS
12
SERIAL
LVDS
12
SERIAL
LVDS
12
SERIAL
LVDS
12
SERIAL
LVDS
DATA RATE
MULTIPLIER
D+A
D–A
D+B
D–B
D+C
D–C
D+D
D–D
D+E
D–E
D+F
D–F
D+G
D–G
D+H
D–H
FCO +
FCO –
DCO +
DCO –
RBIAS
AGND CSB
SDIO/ SCLK/
ODM DTP
Figure 1.
CLK+
CLK–
The ADC contains several features designed to maximize
flexibility and minimize system cost, such as programmable
clock and data alignment and programmable digital test pattern
generation. The available digital test patterns include built-in
deterministic and pseudorandom patterns, along with custom user-
defined test patterns entered via the serial port interface (SPI).
The AD9222 is available in an RoHS compliant, 64-lead LFCSP. It is
specified over the industrial temperature range of −40°C to +85°C.
PRODUCT HIGHLIGHTS
1. Small Footprint. Eight ADCs are contained in a small,
space-saving package.
2. Low power of 114 mW/channel at 65 MSPS.
3. Ease of Use. A data clock output (DCO) is provided that
operates at frequencies of up to 390 MHz and supports
double data rate (DDR) operation.
4. User Flexibility. The SPI control offers a wide range of
flexible features to meet specific system requirements.
5. Pin-Compatible Family. This includes the AD9212 (10-bit)
and AD9252 (14-bit).
Rev. F
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibilityisassumedbyAnalogDevices for itsuse,nor foranyinfringementsofpatentsor other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarksandregisteredtrademarksarethepropertyoftheirrespectiveowners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
www.analog.com
Fax: 781.461.3113 ©2006–2011 Analog Devices, Inc. All rights reserved.
Data Sheet
AD9222
SPECIFICATIONS
AVDD = 1.8 V, DRVDD = 1.8 V, 2 V p-p differential input, 1.0 V internal reference, AIN = −0.5 dBFS, unless otherwise noted.
Table 1.
Parameter 1
RESOLUTION
ACCURACY
No Missing Codes
Offset Error
Offset Matching
Gain Error
Gain Matching
Differential Nonlinearity (DNL)
Integral Nonlinearity (INL)
TEMPERATURE DRIFT
Offset Error
Gain Error
Reference Voltage (1 V Mode)
REFERENCE
Output Voltage Error (VREF = 1 V)
Load Regulation @ 1.0 mA (VREF = 1 V)
Input Resistance
ANALOG INPUTS
Differential Input Voltage Range
(VREF = 1 V)
Common-Mode Voltage
Differential Input Capacitance
Analog Bandwidth, Full Power
POWER SUPPLY
AVDD
DRVDD
IAVDD
IDRVDD
Total Power Dissipation
(Including Output Drivers)
Power-Down Dissipation
Standby Dissipation2
CROSSTALK
CROSSTALK (Overrange Condition)3
Temp
AD9222-40
Min Typ
Max
12
AD9222-50
Min Typ
Max
12
AD9222-65
Min Typ
Max
12
Unit
Bits
Full Guaranteed
Guaranteed
Full ±1 ±8
±1 ±8
Full ±3 ±8
±3 ±8
Full
±0.4 ±1.2
±1.5 ±2.5
Full
±0.3 ±0.7
±0.3 ±0.7
Full
±0.25 ±0.5
±0.3 ±0.65
Full ±0.4 ±1
±0.4 ±1
Guaranteed
±1 ±8
±3 ±8
±3.5 ±5
±0.4 ±0.8
±0.25 ±0.6
±0.4 ±1
mV
mV
% FS
% FS
LSB
LSB
Full ±2
Full ±17
Full ±21
±2
±17
±21
±2 ppm/°C
±17 ppm/°C
±21 ppm/°C
Full
±2 ±30
±2 ±30
Full 3
3
Full 6
6
±2 ±30 mV
3 mV
6 kΩ
Full 2
Full AVDD/2
Full 7
Full 325
2
AVDD/2
7
325
2
AVDD/2
7
325
V p-p
V
pF
MHz
Full 1.7 1.8
Full 1.7 1.8
Full 338
Full 51
Full 700
Full 2
Full 83
Full −90
Full −90
1.9
1.9
348.5
53.6
722
1.7
1.7
11
1.8
1.8
357.5
53.5
740
2
89
−90
−90
1.9
1.9
367.5
56.2
760
11
1.7 1.8
1.7 1.8
450
56.6
910
2
100
−90
−90
1.9
1.9
470
60.5
950.5
V
V
mA
mA
mW
11 mW
mW
dB
dB
1 See the AN-835 Application Note, Understanding High Speed ADC Testing and Evaluation, for a complete set of definitions and how these tests were completed.
2 This can be controlled via SPI.
3 Overrange condition is specific with 6 dB of the full-scale input range.
Rev. F | Page 3 of 60
4페이지 AD9222
Data Sheet
SWITCHING SPECIFICATIONS
AVDD = 1.8 V, DRVDD = 1.8 V, 2 V p-p differential input, 1.0 V internal reference, AIN = −0.5 dBFS, unless otherwise noted.
Table 4.
Parameter1
CLOCK2
Maximum Clock Rate
Minimum Clock Rate
Clock Pulse Width High (tEH)
Clock Pulse Width Low (tEL)
OUTPUT PARAMETERS2, 3
Propagation Delay (tPD)
Rise Time (tR) (20% to 80%)
Fall Time (tF) (20% to 80%)
FCO Propagation Delay (tFCO)
DCO Propagation Delay (tCPD)4
DCO to Data Delay (tDATA)4
DCO to FCO Delay (tFRAME)4
Data to Data Skew
(tDATA-MAX − tDATA-MIN)
Wake-Up Time (Standby)
Wake-Up Time (Power-Down)
Pipeline Latency
APERTURE
Aperture Delay (tA)
Aperture Uncertainty (Jitter)
Out-of-Range Recovery Time
Temp
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
25°C
25°C
Full
25°C
25°C
25°C
AD9222-40
Min Typ Max
40
10
12.5
12.5
1.5
1.5
(tSAMPLE/24)
− 300
(tSAMPLE/24)
− 300
2.3
300
300
2.3
tFCO +
(tSAMPLE/24)
(tSAMPLE/24)
(tSAMPLE/24)
±50
3.1
3.1
(tSAMPLE/24)
+ 300
(tSAMPLE/24)
+ 300
±200
600
375
8
750
<1
1
AD9222-50
Min Typ Max
50
10
10.0
10.0
1.5
1.5
(tSAMPLE/24)
− 300
(tSAMPLE/24)
− 300
2.3
300
300
2.3
tFCO +
(tSAMPLE/24)
(tSAMPLE/24)
(tSAMPLE/24)
±50
3.1
3.1
(tSAMPLE/24)
+ 300
(tSAMPLE/24)
+ 300
±200
600
375
8
750
<1
1
AD9222-65
Min Typ Max
65
10
7.5
7.5
1.5
1.5
(tSAMPLE/24)
− 300
(tSAMPLE/24)
− 300
2.3
300
300
2.3
tFCO +
(tSAMPLE/24)
(tSAMPLE/24)
(tSAMPLE/24)
±50
3.1
3.1
(tSAMPLE/24)
+ 300
(tSAMPLE/24)
+ 300
±200
600
375
8
750
<1
1
Unit
MSPS
MSPS
ns
ns
ns
ps
ps
ns
ns
ps
ps
ps
ns
μs
CLK
cycles
ps
ps
rms
CLK
cycles
1 See the AN-835 Application Note, Understanding High Speed ADC Testing and Evaluation, for a complete set of definitions and how these tests were completed.
2 This can be adjusted via the SPI interface.
3 Measurements were made using a part soldered to FR4 material.
4 tSAMPLE/24 is based on the number of bits divided by 2 because the delays are based on half duty cycles.
Rev. F | Page 6 of 60
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DataSheet.kr | 2020 | 연락처 | 링크모음 | 검색 | 사이트맵 |