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PDF ADS8328 Data sheet ( Hoja de datos )
| Número de pieza | ADS8328 | |
| Descripción | (ADS8327 / ADS8328) ANALOG-TO-DIGITAL CONVERTERS | |
| Fabricantes | Burr-Brown | |
| Logotipo |  |
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BurrĆBrown Products
from Texas Instruments
ADS8327
ADS8328
SLAS415A – APRIL 2006 – REVISED MAY 2006
LOW POWER, 16-BIT, 500-kHz, SINGLE/DUAL UNIPOLAR INPUT, ANALOG-TO-DIGITAL
CONVERTERS WITH SERIAL INTERFACE
FEATURES
• 2.7-V to 5.5-V Analog Supply, Low Power:
– 10.6 mW (+VA = 2.7 V, +VBD = 1.8 V)
• 500-kHz Sampling Rate
• Excellent DC Performance
– ±1.2 LSB Typ, ±2 LSB Max INL
– ±0.6 LSB Typ, ±1 LSB Max DNL
– 16-Bit NMC Over Temperature
– ±0.5 mV Max Offset Error at 2.7 V
– ±1 mV Max Offset Error at 5 V
• Excellent AC Performance at fi = 10 kHz with
91 dB SNR, 101 dB SFDR, –98 dB THD
• Built-In Conversion Clock (CCLK)
• 1.65 V to 5.5 V I/O Supply
– SPI/DSP Compatible Serial
– SCLK up to 50 MHz
• Comprehensive Power-Down Modes:
– Deep Powerdown
– Nap Powerdown
– Auto Nap Powerdown
• Unipolar Input Range: 0 V to Vref
• Software Reset
• Global CONVST (Independent of CS)
• Programmable Status/Polarity EOC/INT
• 16-Pin TSSOP Package
• Multi-Chip Daisy Chain Mode
• Programmable TAG Bit Output
• Manual/Auto Channel Select Mode (ADS8328)
APPLICATIONS
• Communications
• Transducer Interface
• Medical Instruments
• Magnetometers
• Industrial Process Control
• Data Acquisition Systems
• Automatic Test Equipment
DESCRIPTION
The ADS8327 is a low power, 16-bit, 500-ksps
analog-to-digital converter with a unipolar input. The
device includes a 16-bit capacitor-based SAR A/D
converter with inherent sample and hold.
The ADS8328 is based on the same core and
includes a 2-to-1 input MUX with programmable
option of TAG bit output. Both the ADS8327 and
ADS8328 offer a high-speed, wide voltage serial
interface and are capable of chain mode operation
when multiple converters are used.
These converters are available in a 16-lead TSSOP
package and are fully specified for operation over the
industrial -40°C to +85°C temperature range.
Low Power, High-Speed SAR Converter Family
Type/Speed
16 Bit Pseudo-Diff
Single
Dual
500 kHz
ADS8327
ADS8328
1 MHz
ADS8329
ADS8330
ADS8328 ADS8327
+IN1
NC
+IN0
COM
+IN
−IN
REF+
REF−
SAR
OUTPUT
LATCH
SDO
and
3−STATE
DRIVER
+
_
CDAC
COMPARATOR
CONVERSION
and
CONTROL
FS/CS
SCLK
SDI
OSC
LOGIC
CONVST
EOC/INT/CDI
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2006, Texas Instruments Incorporated
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ADS8327
ADS8328
SLAS415A – APRIL 2006 – REVISED MAY 2006
SPECIFICATIONS
TA = –40°C to 85°C, +VA = 5 V, +VBD = +5.5 V to +1.65 V, Vref = 4.096 V, fSAMPLE = 500 kHz (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN TYP
MAX UNIT
ANALOG INPUT
Full-scale input voltage (1)
Absolute input voltage
+IN – (–IN) or (+INx – COM)
+IN, +IN0, +IN1
–IN or COM
0
AGND – 0.2
AGND – 0.2
+Vref
+VA + 0.2
AGND + 0.2
V
V
Input capacitance
40 45 pF
Input leakage current
No ongoing conversion,
DC Input
-1 1 nA
Input channel isolation, ADS8328 only
SYSTEM PERFORMANCE
At dc
VI = ±1.25 Vpp at 50 kHz
109
dB
101
Resolution
16 Bits
No missing codes
16 Bits
ADS8327IB,
INL Integral linearity ADS8328IB
ADS8327I, ADS8328I
–2 ±1.5
-3 ±2
2
LSB (2)
3
DNL
Differential
linearity
ADS8327IB,
ADS8328IB
ADS8327I, ADS8328I
– 1 ±0.7
–1 ±1
1
LSB (2)
2
ADS8327IB,
EO Offset error(3) ADS8328IB
ADS8327I, ADS8328I
–1
–1.25
±0.4
±0.4
1
1.25
mV
Offset error drift
0.5 PPM/°C
EG Gain error
Gain error drift
– 0.25
–0.07
0.3
0.25 %FSR
PPM/°C
CMRR Common mode rejection ratio
Noise
At dc
VI = 1 Vpp at 1 MHz
70
dB
50
33 µV RMS
PSRR Power supply rejection ratio
At FFFFh output code(3)
78 dB
SAMPLING DYNAMICS
tCONV
tSAMPLE
1
tSAMPLE
2
Conversion time
Acquisition time
Throughput rate
Manual trigger
Auto trigger
18
3
3
CCLK
CCLK
500 kHz
Aperture delay
5 ns
Aperture jitter
10 ps
Step response
100 ns
Overvoltage recovery
100 ns
(1) Ideal input span, does not include gain or offset error.
(2) LSB means least significant bit
(3) Measured relative to an ideal full-scale input [+IN – (–IN)] of 4.096 V when +VA = 5 V.
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MANUAL TRIGGER / READ While Sampling
(use internal CCLK, EOC and INT polarity programmed as active low)
ADS8327
ADS8328
SLAS415A – APRIL 2006 – REVISED MAY 2006
CONVST
Nth
twL(CONVST)
EOC
(active low)
tSAMPLE1 = 3 CCLKs min
INT
(active low)
CS/FS
SCLK
th(CSF-EOC)
th(CSF-EOS)
SDO
Nth
tCONV = 18 CCLKs
tSAMPLE1 = 3 CCLKs min
th(CSR-EOS)
tsu(CSF-EOC)
1 . . . . . . . . . . . . . . . . . . . . 16
Nth−1th
th(CSF-EOC)
td(CRS-EOS) = 20 ns min
tsu(CSF-EOS)
1
Nth
SDI
1101b
READ Result
1101b
READ Result
Figure 1. Timing for Conversion and Acquisition Cycles for Manual Trigger (read while sampling)
AUTO TRIGGER / READ While Sampling
(use internal CCLK, EOC and INT polarity programmed as active low)
CONVST = 1
EOC
(active low)
Nth
INT
(active low)
CS/FS
tCONV = 18 CCLKs
tSAMPLE2 = 3 CCLKs
tCONV = 18 CCLKs
th(CSF-EOC)
tsu(CSF-EOS)
th(CSF-EOS)
tSAMPLE2 = 3 CCLKs
tsu(CSF-EOS)
SCLK
SDO
1 . . . . . . . . . . . . . . . . . . .16
N − 1th
1 . . . . . . . . . . . . . . . . . . .16
N − 1th
th(CSF-EOC)
1
Nth
SDI 1110b. . . . . . . . . . . . . .
CONFIGURE
1101b
READ Result
1101b
READ Result
Figure 2. Timing for Conversion and Acquisition Cycles for Autotrigger (read while sampling)
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11
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| Páginas | Total 30 Páginas | |
| PDF Descargar | [ Datasheet ADS8328.PDF ] | |
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