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CS5530 데이터시트 PDF




Cirrus Logic에서 제조한 전자 부품 CS5530은 전자 산업 및 응용 분야에서
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부품번호 CS5530 기능
기능 24-Bit ADC
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CS5530 데이터시트, 핀배열, 회로
CS5530
24-bit ADC with Ultra-low-noise Amplifier
Features & Description
Chopper-stabilized Instrumentation
Amplifier, 64X
• 12 nV/Hz @ 0.1 Hz (No 1/f noise)
• 1200 pA Input Current
Digital Gain Scaling up to 40x
Delta-sigma Analog-to-digital Converter
• Linearity Error: 0.0015% FS
• Noise Free Resolution: Up to 19 bits
Scalable VREF Input: Up to Analog Supply
Simple Three-wire Serial Interface
• SPI™ and Microwire™ Compatible
• Schmitt-trigger on Serial Clock (SCLK)
Onboard Offset and Gain Calibration
Registers
Selectable Word Rates: 6.25 to 3,840 Sps
Selectable 50 or 60 Hz Rejection
Power Supply Configurations
• VA+ = +5 V; VA- = 0 V; VD+ = +3 V to +5 V
• VA+ = +2.5 V; VA- = -2.5 V; VD+ = +3 V to +5 V
• VA+ = +3 V; VA- = -3 V; VD+ = +3 V
General Description
The CS5530 is a highly integrated ΔΣ Analog-to-Digital
Converter (ADC) which uses charge-balance techniques
to achieve 24-bit performance. The ADC is optimized for
measuring low-level unipolar or bipolar signals in weigh
scale, process control, scientific, and medical
applications.
To accommodate these applications, the ADC includes
a very-low-noise, chopper-stabilized instrumentation
amplifier (12 nV/Hz @ 0.1 Hz) with a gain of 64X. This
device also includes a fourth-order ΔΣ modulator fol-
lowed by a digital filter which provides twenty selectable
output word rates of 6.25, 7.5, 12.5, 15, 25, 30, 50, 60, 100,
120, 200, 240, 400, 480, 800, 960, 1600, 1920, 3200, and
3840 Sps (MCLK = 4.9152 MHz).
To ease communication between the ADC and a micro-
controller, the converter includes a simple three-wire se-
rial interface which is SPI and Microwire compatible with
a Schmitt-trigger input on the serial clock (SCLK).
High dynamic range, programmable output rates, and
flexible power supply options make this device an ideal
solution for weigh scale and process control
applications.
ORDERING INFORMATION
See page 35.
VA+ C1
C2
VREF+ VREF-
VD+
AIN1+
AIN1-
64X
DIFFERENTIAL
4TH ORDER ΔΣ
MODULATOR
PROGRAMMABLE
SINC FIR FILTER
SERIAL
INTERFACE
CS
SDI
SDO
SCLK
VA-
http://www.cirrus.com
LATCH
A0 A1
CLOCK
GENERATOR
OSC1 OSC2
CALIBRATION
SRAM/CONTROL
LOGIC
DGND
Copyright Cirrus Logic, Inc. 2009
(All Rights Reserved)
NOV ‘09
DS742F3




CS5530 pdf, 반도체, 판매, 대치품
1. CHARACTERISTICS AND SPECIFICATIONS
ANALOG CHARCTERISTICS
(VA+, VD+ = 5 V ±5%; VREF+ = 5 V; VA-, VREF-, DGND = 0 V; MCLK = 4.9152 MHz;
OWR (Output Word Rate) = 60 Sps; Bipolar Mode)
(See Notes 1 and 2.)
CS5530
Accuracy
Linearity Error
No Missing Codes
Bipolar Offset
Unipolar Offset
Offset Drift
Bipolar full-scale Error
Unipolar full-scale Error
full-scale Drift
Parameter
CS5530-CS
Min Typ
Max
Unit
(Notes 3 and 4)
(Note 4)
-
24
-
-
-
-
-
-
±0.0015
-
±16
±32
10
±8
±16
2
±0.003
-
±32
±64
-
±31
±62
-
%FS
Bits
LSB24
LSB24
nV/°C
ppm
ppm
ppm/°C
Notes: 1. Applies after system calibration at any temperature within -40 °C to +85 °C.
2. Specifications guaranteed by design, characterization, and/or test. LSB is 24 bits.
3. This specification applies to the device only and does not include any effects by external parasitic
thermocouples.
4. Drift over specified temperature range after calibration at power-up at 25 °C.
4 DS742F3

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CS5530 전자부품, 판매, 대치품
CS5530
5 V DIGITAL CHARACTERISTICS
(VA+, VD+ = 5 V ±5%; VA-, DGND = 0 V; See Notes 2 and 11.)
Parameter
High-Level Input Voltage
All Pins Except SCLK
SCLK
Low-Level Input Voltage
All Pins Except SCLK
SCLK
High-Level Output Voltage
A0 and A1, Iout = -1.0 mA
SDO, Iout = -5.0 mA
Low-Level Output Voltage
A0 and A1, Iout = 1.0 mA
SDO, Iout = 5.0 mA
Input Leakage Current
SDO 3-State Leakage Current
Digital Output Pin Capacitance
Symbol
VIH
VIL
VOH
VOL
Iin
IOZ
Cout
Min
0.6 VD+
(VD+) - 0.45
0.0
0.0
(VA+) - 1.0
(VD+) - 1.0
Typ
-
-
-
-
--
- ±1
--
-9
Max
VD+
VD+
0.8
0.6
-
(VA-) + 0.4
0.4
±10
±10
-
Unit
V
V
V
V
µA
µA
pF
3 V DIGITAL CHARACTERISTICS
(TA = 25 °C; VA+ = 5V ±5%; VD+ = 3.0V±10%; VA-, DGND = 0V; See Notes 2 and 11.)
Parameter
High-Level Input Voltage
All Pins Except SCLK
SCLK
Low-Level Input Voltage
All Pins Except SCLK
SCLK
High-Level Output Voltage
A0 and A1, Iout = -1.0 mA
SDO, Iout = -5.0 mA
Low-Level Output Voltage
A0 and A1, Iout = 1.0 mA
SDO, Iout = 5.0 mA
Input Leakage Current
SDO 3-State Leakage Current
Digital Output Pin Capacitance
Symbol
VIH
VIL
VOH
VOL
Iin
IOZ
Cout
Min
0.6 VD+
(VD+) - 0.45
0.0
0.0
(VA+) - 1.0
(VD+) - 1.0
Typ
-
-
-
--
- ±1
--
-9
Max
VD+
VD+
0.8
0.6
-
(VA-) + 0.4
0.4
±10
±10
-
11. All measurements performed under static conditions.
Unit
V
V
V
V
µA
µA
pF
DS742F3
7

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