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PDF PCA9545A Data sheet ( Hoja de datos )
| Número de pieza | PCA9545A | |
| Descripción | 4-channel I2C switch | |
| Fabricantes | NXP Semiconductors | |
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PCA9545A
4-channel I2C switch with interrupt logic and reset
Rev. 03 — 3 March 2005
Product data sheet
1. General description
The PCA9545A is a quad bi-directional translating switch controlled via the I2C-bus. The
SCL/SDA upstream pair fans out to four downstream pairs, or channels. Any individual
SCx/SDx channel or combination of channels can be selected, determined by the
contents of the programmable control register. Four interrupt inputs, INT0 to INT3, one for
each of the downstream pairs, are provided. One interrupt output, INT, acts as an AND of
the four interrupt inputs.
An active LOW reset input allows the PCA9545A to recover from a situation where one of
the downstream I2C-buses is stuck in a LOW state. Pulling the RESET pin LOW resets the
I2C-bus state machine and causes all the channels to be deselected as does the internal
Power-on reset function.
The pass gates of the switches are constructed such that the VDD pin can be used to limit
the maximum high voltage which will be passed by the PCA9545A. This allows the use of
different bus voltages on each pair, so that 1.8 V or 2.5 V or 3.3 V parts can communicate
with 5 V parts without any additional protection. External pull-up resistors pull the bus up
to the desired voltage level for each channel. All I/O pins are 5 V tolerant.
2. Features
s 1-of-4 bi-directional translating switches
s I2C-bus interface logic; compatible with SMBus standards
s 4 active LOW interrupt inputs
s Active LOW interrupt output
s Active LOW reset input
s 2 address pins allowing up to 4 devices on the I2C-bus
s Channel selection via I2C-bus, in any combination
s Power-up with all switch channels deselected
s Low Ron switches
s Allows voltage level translation between 1.8 V, 2.5 V, 3.3 V and 5 V buses
s No glitch on power-up
s Supports hot insertion
s Low stand-by current
s Operating power supply voltage range of 2.3 V to 5.5 V
s 5 V tolerant Inputs
s 0 kHz to 400 kHz clock frequency
s ESD protection exceeds 2000 V HBM per JESD22-A114, 200 V MM per
JESD22-A115, and 1000 V CDM per JESD22-C101
s Latch-up protection exceeds 100 mA per JESD78
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Philips Semiconductors
PCA9545A
4-channel I2C switch with interrupt logic and reset
Table 3:
Symbol
SC1
VSS
INT2
SD2
SC2
INT3
SD3
SC3
INT
SCL
SDA
VDD
Pin description …continued
Pin
SO, TSSOP HVQFN
97
10 8 [1]
11 9
12 10
13 11
14 12
15 13
16 14
17 15
18 16
19 17
20 18
Description
serial clock 1
supply ground
active LOW interrupt input 2
serial data 2
serial clock 2
active LOW interrupt input 3
serial data 3
serial clock 3
active LOW interrupt output
serial clock line
serial data line
supply voltage
[1] HVQFN package die supply ground is connected to both the VSS pin and the exposed center pad. The VSS
pin must be connected to supply ground for proper device operation. For enhanced thermal, electrical, and
board-level performance, the exposed pad needs to be soldered to the board using a corresponding
thermal pad on the board, and for proper heat conduction through the board thermal vias need to be
incorporated in the PCB in the thermal pad region.
7. Functional description
Refer to Figure 1 “Block diagram of PCA9545A” on page 3.
7.1 Device address
Following a START condition, the bus master must output the address of the slave it is
accessing. The address of the PCA9545A is shown in Figure 5. To conserve power, no
internal pull-up resistors are incorporated on the hardware selectable address pins and
they must be pulled HIGH or LOW.
1 1 1 0 0 A1 A0 R/W
fixed
hardware
selectable
002aab169
Fig 5. Slave address
The last bit of the slave address defines the operation to be performed. When set to
logic 1, a read is selected while a logic 0 selects a write operation.
9397 750 14311
Product data sheet
DataSheet4 U .com
Rev. 03 — 3 March 2005
© Koninklijke Philips Electronics N.V. 2005. All rights reserved.
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Philips Semiconductors
PCA9545A
4-channel I2C switch with interrupt logic and reset
8.5 Bus transactions
Data is transmitted to the PCA9545A control register using the Write mode as shown in
Figure 12.
slave address
control register
SDA S 1 1 1 0 0 A1 A0 0 A X X X X B3 B2 B1 B0 A P
START condition
R/W acknowledge
from slave
acknowledge
from slave
STOP condition
002aab172
Fig 12. Write control register
Data is read from PCA9545A using the Read mode as shown in Figure 13.
slave address
control register
last byte
SDA S 1 1 1 0 0 A1 A0 1 A INT3 INT2 INT1 INT0 B3 B2 B1 B0 NA P
START condition
Fig 13. Read control register
R/W acknowledge
from slave
no acknowledge
from master
STOP condition
002aab173
9397 750 14311
Product data sheet
DataSheet4 U .com
Rev. 03 — 3 March 2005
© Koninklijke Philips Electronics N.V. 2005. All rights reserved.
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