|
|
PDF TMPR3927 Data sheet ( Hoja de datos )
| Número de pieza | TMPR3927 | |
| Descripción | PCI Controller | |
| Fabricantes | Toshiba | |
| Logotipo |  |
|
Hay una vista previa y un enlace de descarga de TMPR3927 (archivo pdf) en la parte inferior de esta página. Total 38 Páginas | ||
|
No Preview Available !
www.DataSheet4U.com
TX3927
TMPR3927 Specification Update
Revision History
23-May-2001
04-Oct-2001
30-Oct-2002
22-Jan-2002
05-Jul-2003
14-Mar-2003
19-July-2006
rev1.0
rev1.1
rev1.2
rev1.3
rev1.4
rev1.5
rev1.6
Initial release (up to ERT-TX3927-008)
Added ERT-TX3927-009 and ERT-TX3927-010
Added CE* to ERT-TX3927-008.
Added the table “Summary of the Differences Among Versions of the
TX3927.”
Added descriptions to the Document Changes table.
Deleted condition 3 of ERT-TX3927-008.
Modified the description for WinCE in ERT-TX3927-009.
Added descriptions to the Document Changes table.
Added a description of TMPR3927CF.
Added ERT-TX3927-011 to ERT-TX3927-014.
Added ERT-TX3927-015 to ERT-TX3927-017.
Modified a note showing product types in ERT-TX3927-009.
Added descriptions to the Document Changes table.
Changed Hard Hat Linux to Monta Vista Linux.
Added ERT-TX3927-018.
Added descriptions to the Document Changes table.
Added ERT-TX3927-019.
Modified some references to the related documents.
Deleted the Document Changes table.
This specification update will be incorporated into the next revision of the documents.
Product Types:
TMPR3927F, TMPR3927AF, TMPR3927BF, TMPR3927CF
Related Documents:
TX39 Family TMPR3927 DataBook (2003): Doc. No = BDE0016A
TX39/H2 Processor Core Architecture (2000): Doc. No = 44124D-9908
DataSheet4 U .com
-1-
1 page  
www.DataSheet4U.com
TX3927
ERT-TX3927-004
Product Types: TMPR3927F, TMPR3927AF, (TMPR3927BF, TMPR3927CF)
Note: Although this problem has been fixed in the TMPR3927BF/CF, there are
some usage limitations.
Condition:
Using the PCI Controller in Target mode
Outline
Under particular conditions, the PCI Controller in the TX3927 may assert the STOP* signal unnecessarily
when the PCI bus is idle.
Symptoms
As shown in Figure 1 below, the PCI Controller in the TX3927 may, under particular conditions, assert the
STOP* signal unnecessarily exactly when the PCI bus is idle. The external PCI master may be affected by
this STOP* signal.
Conditions
PCICLK
External
PCI Master
FRAME**
IRDY**
TRDY**
TX3927 DEVSEL**
STOP**
Normal Case
a.
Unnecessary STOP** Signal
Figure 1 Unnecessary assertion of the STOP* signal
When the TX3927 PCI Controller is operating in Target mode and an external PCI master is bursting to the
TX3927, the TX3927 PCI Controller asserts the STOP* signal unnecessarily when the completion of the
burst cycle (a in the above figure) coincides with particular conditions of the TX3927.
There are the following three conditions:
DataSheet4 U .com
-5-
5 Page 
www.DataSheet4U.com
TX3927
Product Types: TMPR3927F, TMPR3927AF, TMPR3927BF, TMPR3927CF
ERT-TX3927-007
Condition:
Using the PCI Controller
Outline
Under particular conditions, the processing of a bus error exception that occurs during a PCI configuration
read doesn’t work correctly.
Bus error exceptions due to other causes are processed properly.
Symptom
When the following conditions are true, the processing of a bus error exception doesn’t work properly.
Conditions
This error occurs when all of the following conditions are true:
1) Timeout error is enabled. That is, the TOE bit of the Chip Configuration (CCFG) register is set to
1.
2) A PCI configuration read is executed in Direct mode. That is, it is executed via the Initiator
Configuration Data Register (ICDR) at 0xFFFE_D13C and the Initiator Configuration Address
Register (ICAR) at 0xFFFE_D138.
A PCI configuration write causes no error.
3) A bus error exception occurs due to a G-Bus timeout. It occurs under the following conditions:
a) The target PCI device repeats the “Retry” because its initialization is incomplete, etc. (i.e.,
repeats the “Retry” via the STOP* signal without asserting the TREADY signal)
b) The PCI bus is deadlocked because the TX3927 and target PCI device repeat the “Retry” with
each other. (This might occur in systems in which the TX3927 is configured to operate in both
Target and Initiator modes. See page 12-84 of the TX3927 databook.)
c) The TX3927 couldn’t receive an acknowledge from the target PCI device within 512 G-Bus
clock cycles because the PCI bus traffic is crowded.
Workarounds
There are two workarounds for this problem. Use either one of them.
1) Execute a PCI configuration read in Indirect mode.
The Indirect mode can be executed by using the following registers:
• Initiator Indirect Address register (IPCIADDR) at 0xFFFE_D150
• Initiator Indirect Data register (IPCIDAT) at 0xFFFE_D154
• Initiator Indirect Command/Byte Enable register (IPCICBE) at 0xFFFE_D158
• Initiator Status register (ISTAT) at 0xFFFE_D044
DataSheet4 U .com
- 11 -
11 Page | ||
| Páginas | Total 38 Páginas | |
| PDF Descargar | [ Datasheet TMPR3927.PDF ] | |
Hoja de datos destacado
| Número de pieza | Descripción | Fabricantes |
| TMPR3922AU | 32-bit RISC Microprocessor |  Toshiba Semiconductor |
| TMPR3927 | PCI Controller | Toshiba |
| Número de pieza | Descripción | Fabricantes |
| SLA6805M | High Voltage 3 phase Motor Driver IC. |
 Sanken |
| SDC1742 | 12- and 14-Bit Hybrid Synchro / Resolver-to-Digital Converters. |
 Analog Devices |
|
DataSheet.es es una pagina web que funciona como un repositorio de manuales o hoja de datos de muchos de los productos más populares, |
| DataSheet.es | 2020 | Privacy Policy | Contacto | Buscar |