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부품번호 ADF4156 기능
기능 6.2 GHz Fractional-N Frequency Synthesizer
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ADF4156 데이터시트, 핀배열, 회로
Data Sheet
6.2 GHz Fractional-N Frequency Synthesizer
ADF4156
FEATURES
RF bandwidth to 6.2 GHz
2.7 V to 3.3 V power supply
Separate VP pin allows extended tuning voltage
Programmable fractional modulus
Programmable charge-pump currents
3-wire serial interface
Digital lock detect
Power-down mode
Pin compatible with ADF4110/ADF4111/ADF4112/ADF4113,
ADF4106, ADF4153, and ADF4154 frequency synthesizers
Programmable RF output phase
Loop filter design possible with ADIsimPLL
Cycle slip reduction for faster lock times
APPLICATIONS
CATV equipment
Base stations for mobile radio (WiMAX, GSM, PCS, DCS,
SuperCell 3G, CDMA, WCDMA)
Wireless handsets (GSM, PCS, DCS, CDMA, WCDMA)
Wireless LANs, PMR
Communications test equipment
GENERAL DESCRIPTION
The ADF4156 is a 6.2 GHz fractional-N frequency synthesizer
that implements local oscillators in the upconversion and down-
conversion sections of wireless receivers and transmitters. It
consists of a low noise digital phase frequency detector (PFD), a
precision charge pump, and a programmable reference divider.
There is a Σ-Δ based fractional interpolator to allow programmable
fractional-N division. The INT, FRAC, and MOD registers define
an overall N divider (N = (INT + (FRAC/MOD))). The RF output
phase is programmable for applications that require a particular
phase relationship between the output and the reference. The
ADF4156 also features cycle slip reduction circuitry, leading
to faster lock times without the need for modifications to the
loop filter.
Control of all on-chip registers is via a simple 3-wire interface.
The device operates with a power supply ranging from 2.7 V to
3.3 V and can be powered down when not in use.
ADF4156
FUNCTIONAL BLOCK DIAGRAM
AVDD DVDD VP
RSET
REFIN
MUXOUT
CE
×2
DOUBLER
5-BIT
R-COUNTER
/2
DIVIDER
HIGH Z
OUTPUT
MUX
VDD
DGND
SDOUT
VDD
RDIV
NDIV
LOCK
DETECT
THIRD-ORDER
FRACTIONAL
INTERPOLATOR
REFERENCE
+ PHASE
FREQUENCY
DETECTOR
CHARGE
PUMP
CURRENT
SETTING
CSR
CP
RFCP4 RFCP3 RFCP2 RFCP1
N-COUNTER
RFINA
RFINB
CLOCK
DATA
LE
32-BIT
DATA
REGISTER
FRACTION MODULUS
REG
REG
INTEGER
REG
AGND
DGND
Figure 1.
CPGND
Rev. E
Document Feedback
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarksandregisteredtrademarksarethepropertyoftheirrespectiveowners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700 ©2006–2013 Analog Devices, Inc. All rights reserved.
Technical Support
www.analog.com




ADF4156 pdf, 반도체, 판매, 대치품
Data Sheet
ADF4156
SPECIFICATIONS
AVDD = DVDD = 2.7 V to 3.3 V, VP = AVDD to 5.5 V, AGND = DGND = 0 V, TA = TMIN to TMAX, dBm referred to 50 Ω, unless otherwise noted.
Table 1.
Parameter
RF CHARACTERISTICS
RF Input Frequency (RFIN)
REFERENCE CHARACTERISTICS
REFIN Input Frequency
REFIN Input Sensitivity
REFIN Input Capacitance
REFIN Input Current
PHASE DETECTOR
Phase Detector Frequency3
CHARGE PUMP
ICP Sink/Source
High Value
Low Value
Absolute Accuracy
RSET Range
ICP Three-State Leakage Current
Matching
ICP vs. VCP
ICP vs. Temperature
LOGIC INPUTS
VINH, Input High Voltage
VINL, Input Low Voltage
IINH/IINL, Input Current
CIN, Input Capacitance
LOGIC OUTPUTS
VOH, Output High Voltage
VOH, Output High Voltage
IOH, Output High Current
VOL, Output Low Voltage
POWER SUPPLIES
AVDD
DVDD
VP
IDD
Low Power Sleep Mode
NOISE CHARACTERISTICS
Normalized Phase Noise Floor (PNSYNTH)4
Normalized 1/f Noise (PN1_f)5
Phase Noise Performance6
5800 MHz Output7
B Version
0.5/6.2
10/250
0.4/AVDD
10
±100
32
Unit
GHz min/max
MHz min/max
V p-p min/max
pF max
µA max
MHz max
5
312.5
2.5
2.7/10
1
2
2
2
1.4
0.6
±1
10
1.4
VDD − 0.4
100
0.4
2.7/3.3
AVDD
AVDD/5.5
32
1
−220
−110
−89
mA typ
µA typ
% typ
kΩ min/max
nA typ
% typ
% typ
% typ
V min
V max
µA max
pF max
V min
V min
µA max
V max
V min/max
V min/max
mA max
µA typ
dBc/Hz typ
dBc/Hz typ
dBc/Hz typ
Test Conditions/Comments1
−10 dBm min to 0 dBm max. For lower frequencies,
ensure slew rate (SR) > 400 V/µs.
For f < 10 MHz, use a dc-coupled CMOS-compatible
square wave, slew rate > 25 V/µs.
Biased at AVDD/2.2
Programmable.
With RSET = 5.1 kΩ.
With RSET = 5.1 kΩ.
Sink and source current.
0.5 V < VCP < VP − 0.5.
0.5 V < VCP < VP − 0.5.
VCP = VP/2.
Open-drain output chosen; 1 kΩ pull-up to 1.8 V.
CMOS output chosen.
IOL = 500 µA.
26 mA typical.
PLL loop BW = 500 kHz. Measured at 100 kHz offset.
10 kHz offset; normalized to 1 GHz.
At VCO output.
At 5 kHz offset, 25 MHz PFD frequency.
1 Operating temperature for B version: −40°C to +85°C.
2 AC coupling ensures AVDD/2 bias.
3 Guaranteed by design. Sample tested to ensure compliance.
4 The synthesizer phase noise floor is estimated by measuring the in-band phase noise at the output of the VCO and subtracting 20 log(N) (where N is the N divider
value) and 10 log(FPFD). PNSYNTH = PNTOT − 10 log(FPFD) − 20 log(N).
5 The PLL phase noise is composed of 1/f (flicker) noise plus the normalized PLL noise floor. The formula for calculating the 1/f noise contribution at an RF frequency, FRF,
and at a frequency offset f is given by PN = PN1_f + 10 log(10 kHz/f) + 20 log(FRF/1 GHz). Both the normalized phase noise floor and flicker noise are modeled in ADIsimPLL.
6 The phase noise is measured with the EV-ADF4156SD1Z evaluation board and the Agilent E5500 phase noise system.
7 fREFIN = 100 MHz, fPFD = 25 MHz, offset frequency = 5 kHz, RFOUT = 5800 MHz, N = 232, loop bandwidth = 20 kHz, ICP = 313 µA, and lowest noise mode.
Rev. E | Page 3 of 24

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ADF4156 전자부품, 판매, 대치품
ADF4156
PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS
Data Sheet
RSET 1
CP 2
CPGND 3
AGND 4
RFINB 5
RFINA 6
AVDD 7
REFIN 8
ADF4156
TOP VIEW
(Not to Scale)
16 VP
15 DVDD
14 MUXOUT
13 LE
12 DATA
11 CLOCK
10 CE
9 DGND
Figure 3. TSSOP Pin Configuration
CPGND 1
AGND 2
AGND 3
RFINB 4
RFINA 5
PIN 1
INDICATOR
ADF4156
TOP VIEW
(Not to Scale)
15 MUXOUT
14 LE
13 DATA
12 CLOCK
11 CE
NOTES
1. THE EXPOSED PAD MUST BE
CONNECTED TO GROUND.
Figure 4. LFCSP Pin Configuration
Table 5. Pin Function Descriptions
Pin No.
TSSOP LFCSP Mnemonic Description
1 19 RSET
Connecting a resistor between this pin and ground sets the maximum charge-pump output current. The
relationship between ICP and RSET is
ICPmax
=
25.5
RSET
where RSET = 5.1 kΩ and ICPmax = 5 mA.
2 20 CP
Charge-Pump Output. When enabled, this pin provides ±ICP to the external loop filter, which in turn drives
the external VCO.
3
1
CPGND
Charge-Pump Ground. This is the ground return path for the charge pump.
4
2, 3 AGND
Analog Ground. This is the ground return path of the prescaler.
5 4 RFINB Complementary Input to the RF Prescaler. Decouple this point to the ground plane with a small bypass
capacitor, typically 100 pF.
6 5 RFINA Input to the RF Prescaler. This small-signal input is normally ac-coupled from the VCO.
7 6, 7 AVDD
Positive Power Supply for the RF Section. Decoupling capacitors to the digital ground plane should be
placed as close as possible to this pin. AVDD has a value of 3 V ± 10%. AVDD must have the same voltage as DVDD.
8 8 REFIN
Reference Input. This is a CMOS input with a nominal threshold of VDD/2 and an equivalent input resistance
of 100 kΩ. This input can be driven from a TTL or CMOS crystal oscillator, or it can be ac-coupled.
9
9, 10 DGND
Digital Ground.
10 11 CE
Chip Enable. A logic low on this pin powers down the device and puts the charge-pump output into
three-state mode.
11 12 CLOCK Serial Clock Input. This serial clock is used to clock in the serial data to the registers. The data is latched
into the shift register on the CLOCK rising edge. This input is a high impedance CMOS input.
12 13 DATA
Serial Data Input. The serial data is loaded MSB first with the three LSBs serving as the control bits. This
input is a high impedance CMOS input.
13 14 LE
Load Enable, CMOS Input. When LE is high, the data stored in the shift registers is loaded into one of the
five latches. The control bits are used to select the latch.
14 15 MUXOUT Multiplexer Output. This multiplexer output allows either the RF lock detect, the scaled RF, or the scaled
reference frequency to be accessed externally.
15 16, 17 DVDD
Positive Power Supply for the Digital Section. Decoupling capacitors to the digital ground plane should be
placed as close as possible to this pin. DVDD has a value of 3 V ± 10%. DVDD must have the same voltage as AVDD.
16 18 VP
Charge-Pump Power Supply. This should be greater than or equal to VDD. In systems where VDD is 3 V, it can
be set to 5.5 V and used to drive a VCO with a tuning range of up to 5.5 V.
EPAD
The exposed pad must be connected to ground.
Rev. E | Page 6 of 24

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