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AD12400 데이터시트 PDF




Analog Devices에서 제조한 전자 부품 AD12400은 전자 산업 및 응용 분야에서
광범위하게 사용되는 반도체 소자입니다.


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부품번호 AD12400 기능
기능 12-Bit 400 MSPS A/D Converter
제조업체 Analog Devices
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AD12400 데이터시트, 핀배열, 회로
12-Bit, 400 MSPS A/D Converter
FEATURES
400 MSPS sample rate
SNR of 63 dBFS @128 MHz
SFDR of 70 dBFS @128 MHz
VSWR of 1:1.5
Wideband ac-coupled input signal conditioning
Enhanced spurious-free dynamic range
Single-ended or differential encode signal
LVDS output levels
Twos complement output data
APPLICATIONS
Communications test equipment
Radar and satellite subsystems
Phased array antennas—digital beam
Multichannel, multimode receivers
Secure communications
Wireless and wired broadband communications
Wideband carrier frequency systems
GENERAL DESCRIPTION
The AD12400 is a 12-bit analog-to-digital converter (ADC)
with a transformer-coupled analog input and digital post-
processing for enhanced SFDR. The product operates at a 400
MSPS conversion rate with outstanding dynamic performance
in wideband carrier systems.
The AD12400 requires 3.8 V analog, 3.3 V digital, and 1.5 V
digital supplies, and provides a flexible encode signal that can
be differential or single-ended. No external reference is
required.
The AD12400 package style is an enclosed 2.9" × 2.6" × 0.6"
module. Performance is rated over a 0°C to 60°C case
temperature range.
AD12400
FUNCTIONAL BLOCK DIAGRAM
AD12400
DATA
READY
A
ADC
A
DA0–DA11
POST-
CLK DISTRIBUTION PROCESSING
AIN
ADC
B
DB0–DB11
CLOCK DISTRIBUTION
DIVIDE BY 2
DATA
READY
B
ENC
ENC
Figure 1.
PRODUCT HIGHLIGHTS
1. Guaranteed sample rate of 400 MSPS.
2. Input signal conditioning with optimized dynamic
performance to 180 MHz.
3. Additional performance options available; contact factory.
4. Proprietary Advanced Filter Bank (AFB™) digital
postprocessing from V Corp Technologies, Inc.
Rev. A
Information furnished by Analog Devices is believed to be accurate and reliable.
However, no responsibility is assumed by Analog Devices for its use, nor for any
infringements of patents or other rights of third parties that may result from its use.
Specifications subject to change without notice. No license is granted by implication
or otherwise under any patent or patent rights of Analog Devices. Trademarks and
registered trademarks are the property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
www.analog.com
Fax: 781.461.3113
©2005 Analog Devices, Inc. All rights reserved.




AD12400 pdf, 반도체, 판매, 대치품
AD12400
AC SPECIFICATIONS1
VA = 3.8 V, VC = 3.3 V, VD = 1.5 V, encode = 400 MSPS, 0°C ≤ TCASE ≤ 60°C, unless otherwise noted.
Table 2.
AD12400JWS
AD12400KWS
Parameter
Case Temp Test Level
Min Typ Max Min Typ Max
DYNAMIC PERFORMANCE2
SNR
Analog Input 10 MHz
Full
I
62 64.4
62 64.4
@ −1.0 dBFS 70 MHz
Full
I
61.5 64
61.5 64
128 MHz
Full
I
60 63.5
60 63.5
SINAD3
180 MHz
Full
I
60 62.5
60 62.5
Analog Input 10 MHz
Full
I
61 64
61 64
@ −1.0 dBFS 70 MHz
Full
I
60.5 64
60.5 64
128 MHz
Full
I
59 62.5
59 62.5
180 MHz
Spurious-Free Dynamic Range3
Full
I
57 61
57 61
Analog Input 10 MHz
Full
I
69 80
69 80
@ −1.0 dBFS 70 MHz
Full
I
69 84
69 84
128 MHz
Full
I
67 76
67 76
Image Spur4
180 MHz
Full
I
62 71
62 71
Analog Input 10 MHz
Full
I
60 75
62 75
@ −1.0 dBFS 70 MHz
Full
I
60 72
62 72
128 MHz
Full
I
56 70
62 70
Offset Spur4
180 MHz
Full
I
54 70
62 70
Analog Input @ −1.0 dBFS
60°C
V
65
65
Two-Tone IMD5
F1, F2 @ −6 dBFS
60°C V
−75 −75
SWITCHING SPECIFICATIONS
Conversion Rate6
Encode Pulse Width High (tEH)1
Encode Pulse Width Low (tEL)1
DIGITAL OUTPUT PARAMETERS
Full
60°C
60°C
IV
V
V
396 400 404
1.25
1.25
396 400 404
1.25
1.25
Valid Time (tV)
Propagation Delay (tPD)
Rise Time (tR) (20% to 80%)
Fall Time (tF) (20% to 80%)
DR Propagation Delay (tEDR)
Data to DR Skew (tEDR − tPD)
Pipeline Latency7
Full
60°C
60°C
60°C
60°C
60°C
Full
IV
V
V
V
V
V
IV
1.9 2.4 3.1
1.20
1
1
3.88
2.68
74
1.9 2.4 3.1
1.20
1
1
3.88
2.68
74
Aperture Delay (tA)
60°C
IV
1.6
1.6
Aperture Uncertainty (Jitter, tJ)
60°C
V
0.4
0.4
Unit
dBFS
dBFS
dBFS
dBFS
dBFS
dBFS
dBFS
dBFS
dBFS
dBFS
dBFS
dBFS
dBFS
dBFS
dBFS
dBFS
dBFS
dBc
MSPS
ns
ns
ns
ns
ns
ns
ns
ns
Cycles
ns
ps rms
1 All ac specifications tested with a single-ended, 2.0 V p-p encode.
2 Dynamic performance guaranteed for analog input frequencies of 10 MHz to 180 MHz.
3 Not including image spur.
4 The image spur is at fs/2 AIN; the offset spur is at fs/2.
5 F1 = 70 MHz, F2 = 73 MHz.
6 Parts are tested with 400 MSPS encode. Device can be clocked at lower encode rates, but specifications are not guaranteed. Specifications are guaranteed by design
for encode 400 MSPS ±1%.
7 Pipeline latency is exactly 74 cycles.
Rev. A | Page 4 of 24

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AD12400 전자부품, 판매, 대치품
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
AD12400
AIN
ENC
ENC
PIN 1
TOP VIEW
PIN 119
VA
VA
VA
VA
AGND
AGND
DNC
DNC
DNC
DNC
DNC
DNC
AGND
AGND
AGND
AGND
AGND
AGND
AGND
AGND
1
VA
PIN 120
VA
VA
VA
AGND
AGND
DNC
DNC
DNC
DNC
DNC
C
DNC
DNC
AGND
AGND
AGND
AGND
AGND
AGND
AGND
JOHNSON SMA-50 OHM CONNECT NO. 142-0711-821
ENC
ENC
2-56 STUDS 4×
END VIEW
SAMTEC CONNECTOR
QTE-060-01-L-D-A-K-TR
BOARD
1
PIN 79
DNC
DRA
PIN 80
LEAD/LAG
DRA
DA1+
DA0+
DA1–
DA0–
DA3+
DA2+
DA3–
DA2–
DA5+
DA4+
DA5–
DA4–
DA7+
DA6+
DA7–
DA6–
B
DA9+
DA8+
DA9–
DA8–
DA11+
DA10+
DA11–
DA10–
DNC
DNC
DNC
PASS
VD VD
VD VD
VD VD
VD VD
PIN 39
AIN
BOTTOM VIEW
LEFT SIDE VIEW
NOTES
1INTEGRAL GROUND PLANE CONNECTIONS.
1. FOR MATING HALF, USE SAMTEC, INC. SECTION A = DGND, PINS 121–124.
PART NO. QSE-60-01-L-D-A-K.
SECTION B = DGND, PINS 125–128.
SECTION C = AGND, PINS 129–132.
PIN 1
DB1+
DB1–
DB3+
DB3–
DB5+
DB5–
DB7+
DB7–
DB9+
DB9–
DB11+
DB11–
DNC
DNC
DNC
DNC
DNC
RESET
VC
VC
1
DB0+
PIN 40
DB0–
DB2+
DB2–
DB4+
DB4–
DB6+
DB6–
DB8+
DB8–
A
DB10+
DB10–
DNC
DNC
DRB
DRB
DNC
DNC
VC
VC PIN 2
Figure 5. Pin Configuration
Table 6. Pin Function Descriptions
Pin No.
Mnemonic
1 to 4
VC
5 RESET
6 to 9, 11, 13 to 16, 49,
51, 52, 79, 96 to 108
10
12
17
18
DNC
DRB
DRB
DB11−
DB10−
Description
Digital Supply, 3.3 V.
LVTTL. 0 = device reset. Minimum width = 200 ns. Device resumes operation after 600 ms
maximum.
Do Not Connect.
Channel B Data Ready. Complement output.
Channel B Data Ready. True output.
Channel B Data Bit 11. Complement output bit.
Channel B Data Bit 10. Complement output bit.
Rev. A | Page 7 of 24

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