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AD12401 데이터시트 PDF




Analog Devices에서 제조한 전자 부품 AD12401은 전자 산업 및 응용 분야에서
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부품번호 AD12401 기능
기능 400 MSPS A/D Converter
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AD12401 데이터시트, 핀배열, 회로
www.DataSheet4U.com
FEATURES
Up to 400 MSPS sample rate
SNR of 63 dBFS @128 MHz
SFDR of 70 dBFS @128 MHz
VSWR of 1:1.5
High or low gain grades
Wideband ac-coupled input signal conditioning
Enhanced spurious-free dynamic range
Single-ended or differential ENCODE signal
LVDS output levels
Twos complement output data
APPLICATIONS
Communications test equipment
Radar and satellite subsystems
Phased array antennas, digital beams
Multichannel, multimode receivers
Secure communications
Wireless and wired broadband communications
Wideband carrier frequency systems
GENERAL DESCRIPTION
The AD12401 is a 12-bit analog-to-digital converter (ADC)
with a transformer-coupled analog input and digital post-
processing for enhanced SFDR. The product operates at up to
400 MSPS conversion rate with outstanding dynamic performance
in wideband carrier systems.
The AD12401 requires a 3.7 V analog supply and 3.3 V and
1.5 V digital supplies, and provides a flexible ENCODE signal
that can be differential or single ended. No external reference is
required.
The AD12401 package style is an enclosed 2.9" × 2.6" × 0.6"
module. Performance is rated over a 0°C to 60°C case
temperature range.
12-Bit, 400 MSPS A/D Converter
AD12401
FUNCTIONAL BLOCK DIAGRAM
AD12401
DATA
READY
A
ADC
A
DA0–DA11
POST-
CLK DISTRIBUTION PROCESSING
DB0–DB11
AIN
ADC
B
DR_EN
CLOCK DISTRIBUTION
DIVIDE BY 2
DATA
READY
B
ENC
ENC
OROUT
Figure 1.
PRODUCT HIGHLIGHTS
1. Guaranteed sample rate up to 400 MSPS.
2. Input signal conditioning with optimized dynamic
performance to 175 MHz.
3. High and low gain grades available.
4. Additional performance options available (sample rates
>400 MSPS or second Nyquist zone operation); contact
sales.
5. Proprietary Advanced Filter Bank (AFB™) digital post-
processing from V Corp Technologies, Inc.
Rev. A
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarksandregisteredtrademarksarethepropertyoftheirrespectiveowners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
www.analog.com
Fax: 781.461.3113
©2006 Analog Devices, Inc. All rights reserved.




AD12401 pdf, 반도체, 판매, 대치품
www.DataSheet4U.com
AD12401
Parameter
LOGIC OUTPUTS (DRA, DRB, OUTPUT BITS)3
Differential Output Voltage
Output Common-Mode Voltage
Output High Voltage
Output Low Voltage
AD12401-xxxKWS
AD12401-xxxJWS
Case Temp Test Level Min Typ
Max Min Typ Max Unit
Full IV
Full IV
60°C IV
60°C IV
247 350
1.125 1.25
0.898
454 247 350 454 mV
1.375 1.125 1.25 1.375 V
1.602
1.602 V
0.898
V
1 Tested using input frequency of 70 MHz (see Figure 17).
2 Refer to Table 8 for logic convention on all logic inputs.
3 Digital output logic levels: VC = 3.3 V, CLOAD = 8 pF, 2.5 V LVDS, RT = 100 Ω.
AC SPECIFICATIONS1—ENCODE = 400 MSPS
VA = 3.7 V, VC = 3.3 V, VD = 1.5 V, ENCODE = 400 MSPS, 0°C ≤ TCASE ≤ 60°C, unless otherwise noted.
Table 2.
Parameter
DYNAMIC PERFORMANCE
SNR
Analog Input 10 MHz
@ −1.0 dBFS 70 MHz
128 MHz
175 MHz
SINAD2
Analog Input 10 MHz
@ −1.0 dBFS 70 MHz
128 MHz
175 MHz
Spurious-Free Dynamic Range3
Analog Input 10 MHz
@ −1.0 dBFS 70 MHz
128 MHz
175 MHz
Image Spur4
Analog Input 10 MHz
@ −1.0 dBFS 70 MHz
128 MHz
175 MHz
Offset Spur4
Analog Input @ −1.0 dBFS
Two-Tone IMD5
F1, F2 @ −6 dBFS
ANALOG INPUT
Frequency Range
DIGITAL INPUT (DR_EN)
Minimum Time (Low)
SWITCHING SPECIFICATIONS
Conversion Rate6
Encode Pulse Width High (tEH)1
Encode Pulse Width Low (tEL)1
Case Temp
Test Level
AD12401-400KWS
AD12401-400JWS
Min Typ Max Min Typ Max
Full I
Full I
Full I
Full I
Full I
Full I
Full I
Full I
Full I
Full I
Full I
Full I
Full I
Full I
Full I
Full I
60°C V
60°C V
Full IV
Full IV
Full IV
60°C V
60°C V
62 64
61.5 63.5
60 63
60 62.5
59 63.5
58.5 63
57.5 61.5
55 60
69 85
69 80
66 72
62 68
60 75
60 72
60 66
57 63
65
−75
10 175
5.0
396 400 404
1.25
1.25
60 62
59.5 61.5
58 61
57.5 60.5
57 61.5
56.5 61
55.5 59.5
53 58
69 85
69 80
66 72
62 68
60 75
60 72
60 66
57 63
65
−75
10 175
5.0
396 400 404
1.25
1.25
Unit
dBFS
dBFS
dBFS
dBFS
dBFS
dBFS
dBFS
dBFS
dBFS
dBFS
dBFS
dBFS
dBFS
dBFS
dBFS
dBFS
dBFS
dBc
MHz
ns
MSPS
ns
ns
Rev. A | Page 4 of 28

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AD12401 전자부품, 판매, 대치품
www.DataSheet4U.com
AD12401
Parameter
ANALOG INPUT
Frequency Range
DIGITAL INPUT (DR_EN)
Minimum Time (Low)
SWITCHING SPECIFICATIONS
Conversion Rate6
Encode Pulse Width High (tEH)1
Encode Pulse Width Low (tEL)1
DIGITAL OUTPUT PARAMETERS
Valid Time (tV)
Propagation Delay (tPD)
Rise Time, tR (20% to 80%)
Fall Time, tF (20% to 80%)
DR Propagation Delay (tEDR)
Data to DR Skew (tEDR − tPD)
Pipeline Latency7
Start-Up Time
Postprocessing Configuration Time
APERTURE DELAY (tA)
APERTURE UNCERTAINTY (Jitter, tJ)
Case Temp
Test Level
AD12401-326KWS
AD12401-326JWS
Min Typ Max Min Typ Max Unit
Full IV
10
140 10
140 MHz
Full IV
6.2
6.2 ns
Full IV
60°C V
60°C V
323 326 329
1.53
1.53
323 326 329
1.53
1.53
MSPS
ns
ns
Full IV
60°C V
60°C V
60°C V
60°C V
60°C V
Full IV
Full IV
Full IV
60°C V
60°C V
5.0 5.0 ns
8.7 8.7 ns
0.3 0.3 ns
0.3 0.3 ns
11.8 11.8 ns
3.1 3.1 ns
74 74 Cycles
29 44 87 29 44 87 ms
3.4 3.4 sec
2.3 2.3 ns
0.4 0.4 ps rms
1 All ac specifications tested with a single-ended, 2.0 V p-p encode on ENCODE and ENCODE floating.
2 The image spur is included in the SINAD measurement.
3 The image spur is not included in the SFDR specification.
4 The image spur is at fS/2 − AIN; the offset spur is at fS/2.
5 F1 = 70 MHz, F2 = 73 MHz.
6 Parts are tested with 326 MSPS encode. Device can be clocked at lower encode rates, but specifications are not guaranteed. Specifications are guaranteed by design
for encode 326 MSPS ±1%.
7 Pipeline latency is exactly 74 cycles with an additional tPD required for data to emerge.
Rev. A | Page 7 of 28

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